micropython · Aug 8, 2019 · Aug 8, 2019 · Aug 8, 2019 · Aug 8, 2019 · Aug 8, 2019
diff --git a/.gitignore b/.gitignore
@@ -19,10 +19,12 @@
 # VIM Swap Files
 ######################
 *.swp
+*.un~
 
 # Build directory
 ######################
 build/
+generated/
 
 # Test failure outputs
 ######################

diff --git a/ports/fupy/Makefile b/ports/fupy/Makefile
@@ -0,0 +1,140 @@
+BUILDINC_DIRECTORY ?= .
+ifeq ($(wildcard $(BUILDINC_DIRECTORY)/generated/variables.mak),)
+define ERROR_MSG
+
+$(BUILDINC_DIRECTORY)/generated/variables.mak not found.
+
+MicroPython for LiteX requires these generated files to build. It
+is important that the files match the gateware you are using and
+are specific to each board / platform.
+
+The LiteX generated files are found in build output directory
+under "software/include/generated".
+
+To allow MicroPython to find these files, you must do one of the
+following;
+ * Set BUILDINC_DIRECTORY.
+ * Copy the files into a local generated directory.
+ * Run ./get-gateware.sh script (setting PLATFORM/TARGET value).
+
+endef
+$(error $(ERROR_MSG))
+endif # no generated/variables.mak
+include $(BUILDINC_DIRECTORY)/generated/variables.mak
+
+include ../../py/mkenv.mk
+
+# qstr definitions (must come before including py.mk)
+QSTR_DEFS = qstrdefsport.h
+
+# include py core make definitions
+include ../../py/py.mk
+
+CROSS_COMPILE ?= $(TRIPLE)-
+
+INC += -I.
+INC += -I../..
+INC += -I../../lib/mp-readline
+INC += -I$(BUILD)
+INC += -I$(BUILDINC_DIRECTORY)
+
+# Ensure assembler can also found our custom include files, for crt0
+ASFLAGS += -I$(BUILDINC_DIRECTORY)
+
+CFLAGS += $(CPUFLAGS)
+CFLAGS += $(INC) -Wall -Werror -std=gnu11 -ggdb $(COPT)
+CFLAGS += -Og -Wdouble-promotion -Wall -Werror
+
+ifneq ($(DEBUG), 1)
+CFLAGS += -DNDEBUG
+endif
+
+ifeq ($(COPY_TO_MAIN_RAM), 1)
+LDFLAGS += -nostartfiles -T litex.ld -Wl,-Map=$@.map -Wl,--cref
+else
+LDFLAGS += -nostartfiles -T litex-flash.ld -Wl,-Map=$@.map -Wl,--cref
+endif
+
+LDFLAGS += -L$(BUILDINC_DIRECTORY)
+LIBS = -Wl,-lc -Wl,-lm
+
+SRC_C = \
+	main.c \
+	uart.c \
+	isr.c \
+	modmachine.c \
+	modlitex.c \
+	litex_leds.c \
+	litex_switches.c \
+	lib/utils/stdout_helpers.c \
+	lib/utils/interrupt_char.c \
+	lib/utils/pyexec.c \
+	lib/libc/string0.c \
+	lib/mp-readline/readline.c
+
+# FIXME: Should use crt0 from newlib? However it seems to cause memory access
+# at 0x0
+
+ifeq ($(COPY_TO_MAIN_RAM), 1)
+CRT0_S ?= $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+CRT0_O = $(BUILD)/crt0-$(CPU)-ctr.o
+CRT0FLAGS =
+else ifeq ($(EXECUTE_IN_PLACE), 1)
+CRT0_S ?= $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+CRT0_O = $(BUILD)/crt0-$(CPU)-xip.o
+CRT0FLAGS = -DEXECUTE_IN_PLACE
+else
+$(error You need to define one of COPY_TO_MAIN_RAM or EXECUTE_IN_PLACE to 1)
+endif
+
+# CPU-specific overrides.
+ifeq ($(CPU), picorv32)
+# Extract the arch-specific flags, otherwise firmware won't link.
+LDFLAGS += $(filter -march=% -mabi=%, $(CPUFLAGS))
+# picorv32 needs a special assembly include to compile crt0.
+ASFLAGS += -I$(SOC_DIRECTORY)/software/include/base
+else ifeq ($(CPU), vexriscv)
+LDFLAGS += $(filter -march=% -mabi=%, $(CPUFLAGS))
+endif
+
+# No extra assembly files for now.
+SRC_S =
+
+OBJ =  $(CRT0_O) $(addprefix $(BUILD)/, $(SRC_S:.S=.o)) $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
+
+all: $(BUILD)/firmware.bin
+
+# List of sources for qstr extraction
+SRC_QSTR += $(SRC_C) $(SRC_LIB)
+
+# crt0 override for normal assembler rule- needed to distinguish
+# whether we need to assemble a crt0 that copies a data section to RAM from
+# flash, or a crt0 that assumes a bootloader does it ahead of time.
+$(CRT0_O): $(CRT0_S)
+	$(CC) -c $(ASFLAGS) $(CFLAGS) $(CRT0FLAGS) -o $@ $<
+
+$(BUILD)/_frozen_mpy.c: frozentest.mpy $(BUILD)/genhdr/qstrdefs.generated.h
+	$(ECHO) "MISC freezing bytecode"
+	$(Q)../tools/mpy-tool.py -f -q $(BUILD)/genhdr/qstrdefs.preprocessed.h -mlongint-impl=none $< > $@
+
+$(BUILD)/firmware.elf: $(OBJ)
+	$(ECHO) "LINK $@"
+	$(Q)$(CC) $(LDFLAGS) -o $@ $^ $(LIBS)
+	$(Q)$(SIZE) $@
+
+$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
+	$(Q)$(OBJCOPY) -O binary $^ $(BUILD)/firmware.bin
+
+# Run emulation build on a POSIX system with suitable terminal settings
+run:
+	stty raw opost -echo
+	build/firmware.elf
+	@echo Resetting terminal...
+# This sleep is useful to spot segfaults
+	sleep 1
+	reset
+
+test: $(BUILD)/firmware.elf
+	$(Q)/bin/echo -e "print('hello world!', list(x+1 for x in range(10)), end='eol\\\\n')\\r\\n\\x04" | $(BUILD)/firmware.elf | tail -n2 | grep "^hello world! \\[1, 2, 3, 4, 5, 6, 7, 8, 9, 10\\]eol"
+
+include ../../py/mkrules.mk
diff --git a/ports/fupy/README.md b/ports/fupy/README.md
@@ -0,0 +1,35 @@
+# The minimal port
+
+This port is intended to be a minimal MicroPython port that actually runs.
+It can run under Linux (or similar) and on any STM32F4xx MCU (eg the pyboard).
+
+## Building and running Linux version
+
+By default the port will be built for the host machine:
+
+    $ make
+
+To run a small test script do:
+
+    $ make run
+
+## Building for an STM32 MCU
+
+The Makefile has the ability to build for a Cortex-M CPU, and by default
+includes some start-up code for an STM32F4xx MCU and also enables a UART
+for communication.  To build:
+
+    $ make CROSS=1
+
+If you previously built the Linux version, you will need to first run
+`make clean` to get rid of incompatible object files.
+
+Building will produce the build/firmware.dfu file which can be programmed
+to an MCU using:
+
+    $ make CROSS=1 deploy
+
+This version of the build will work out-of-the-box on a pyboard (and
+anything similar), and will give you a MicroPython REPL on UART1 at 9600
+baud.  Pin PA13 will also be driven high, and this turns on the red LED on
+the pyboard.
diff --git a/ports/fupy/csr-defs.h b/ports/fupy/csr-defs.h
@@ -0,0 +1,11 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */
diff --git a/ports/fupy/frozentest.mpy b/ports/fupy/frozentest.mpy
diff --git a/ports/fupy/frozentest.py b/ports/fupy/frozentest.py
@@ -0,0 +1,7 @@
+print('uPy')
+print('a long string that is not interned')
+print('a string that has unicode αβγ chars')
+print(b'bytes 1234\x01')
+print(123456789)
+for i in range(4):
+    print(i)
diff --git a/ports/fupy/get-gateware.sh b/ports/fupy/get-gateware.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+PLATFORM="${PLATFORM:-mimasv2}"
+TARGET="${TARGET:-base}"
+CPU="${CPU:-lm32}"
+BRANCH="${BRANCH:-master}"
+
+GITHUB_URL=https://github.com/timvideos/HDMI2USB-firmware-prebuilt/
+
+# Automatically figure out the latest revision
+if [ "$REV" = "" ]; then
+	REV=$(svn ls $GITHUB_URL/trunk/archive/$BRANCH | sort | tail -n1 | sed -e's-/$--')
+	echo "Using revision $REV"
+fi
+
+# archive/master/v0.0.3-696-g2f815c1/minispartan6/base/lm32
+BASE_DIR=archive/$BRANCH/$REV/$PLATFORM/$TARGET/$CPU
+
+# Get the generated header files
+svn export --force $GITHUB_URL/trunk/$BASE_DIR/software/include/generated | grep -v "^Exported"
+
+# Get the flash file
+#svn export --force $SVN_URL/flash.bin
+
+# Get gateware and bios files (to allow image building)
+#svn export --force $SVN_URL/gateware/top.bin gateware.bin
+#svn export --force $SVN_URL/software/bios/bios.bin
diff --git a/ports/fupy/irq.h b/ports/fupy/irq.h
@@ -0,0 +1,144 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+
+#ifdef __picorv32__
+// PicoRV32 has a very limited interrupt support, implemented via custom
+// instructions. It also doesn't have a global interrupt enable/disable, so
+// we have to emulate it via saving and restoring a mask and using 0/~1 as a
+// hardware mask.
+// Due to all this somewhat low-level mess, all of the glue is implemented in
+// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
+// managed by this layer, do not call interrupt instructions directly, as the
+// state will go out of sync with the hardware.
+
+// Read only.
+extern unsigned int _irq_pending;
+// Read only.
+extern unsigned int _irq_mask;
+// Read only.
+extern unsigned int _irq_enabled;
+extern void _irq_enable(void);
+extern void _irq_disable(void);
+extern void _irq_setmask(unsigned int);
+#endif
+
+static inline unsigned int irq_getie(void)
+{
+#if defined (__lm32__)
+	unsigned int ie;
+	__asm__ __volatile__("rcsr %0, IE" : "=r" (ie));
+	return ie;
+#elif defined (__or1k__)
+	return !!(mfspr(SPR_SR) & SPR_SR_IEE);
+#elif defined (__picorv32__)
+	return _irq_enabled != 0;
+#elif defined (__vexriscv__)
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+#elif defined (__minerva__)
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+#else
+#error Unsupported architecture
+#endif
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+#if defined (__lm32__)
+	__asm__ __volatile__("wcsr IE, %0" : : "r" (ie));
+#elif defined (__or1k__)
+	if (ie & 0x1)
+		mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
+	else
+		mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
+#elif defined (__picorv32__)
+    if (ie & 0x1)
+        _irq_enable();
+    else
+        _irq_disable();
+#elif defined (__vexriscv__)
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+#elif defined (__minerva__)
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+#else
+#error Unsupported architecture
+#endif
+}
+
+static inline unsigned int irq_getmask(void)
+{
+#if defined (__lm32__)
+	unsigned int mask;
+	__asm__ __volatile__("rcsr %0, IM" : "=r" (mask));
+	return mask;
+#elif defined (__or1k__)
+	return mfspr(SPR_PICMR);
+#elif defined (__picorv32__)
+    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
+    // LiteX sees things.
+    return ~_irq_mask;
+#elif defined (__vexriscv__)
+	unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return mask;
+#elif defined (__minerva__)
+	unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return mask;
+#else
+#error Unsupported architecture
+#endif
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+#if defined (__lm32__)
+	__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
+#elif defined (__or1k__)
+	mtspr(SPR_PICMR, mask);
+#elif defined (__picorv32__)
+    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
+    // LiteX sees things.
+    _irq_setmask(~mask);
+#elif defined (__vexriscv__)
+	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+#elif defined (__minerva__)
+	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+#else
+#error Unsupported architecture
+#endif
+}
+
+static inline unsigned int irq_pending(void)
+{
+#if defined (__lm32__)
+	unsigned int pending;
+	__asm__ __volatile__("rcsr %0, IP" : "=r" (pending));
+	return pending;
+#elif defined (__or1k__)
+	return mfspr(SPR_PICSR);
+#elif defined (__picorv32__)
+	return _irq_pending;
+#elif defined (__vexriscv__)
+	unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return pending;
+#elif defined (__minerva__)
+	unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return pending;
+#else
+#error Unsupported architecture
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/ports/fupy/isr.c b/ports/fupy/isr.c
@@ -0,0 +1,13 @@
+#include <generated/csr.h>
+#include <irq.h>
+#include <uart.h>
+
+void isr(void)
+{
+	unsigned int irqs;
+
+	irqs = irq_pending() & irq_getmask();
+
+	if(irqs & (1 << UART_INTERRUPT))
+		uart_isr();
+}