Add an arch for RISCV with vector extension

[michael-roe]

No description provided.

[drom]

It would be cool porting Volk on RVV
I want to be part of it.

[jdemel]

I'd be in favor of adding RiscV support for VOLK. Also, we already run QA tests for RiscV and we already have some hand optimized assembly for this ISA. Though, no vector support for it.
As far as I know it is very difficult to get RiscV systems with vector extensions.

This PR in particular is difficult though because riscv_vector ends up in the list of x86 extensions. Also, I thought this PR was closed in favor of a later one.

[drom]

RISC-V Vector v1.0 (RVV1) looks like perfect fit for Volk.
We will see ICs with RVV1 in the near future. For now we can use simulator.
I can help with cycle accurate profiling on RVV cores that SiFive provides.

[jdemel]

Is riscv_vector a good name for this architecture? The RiscV naming system is getting a bit confusing.

[drom]

RISC-V has naming convention (ISA-string) described in the spec:
https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
Chapter 22. Page 121

I think the baseline Vector ISA for this project should be RV64I2p0M2p0A2p0F2p0D2p0V1p0
can be checked here: https://rv.drom.io/?RV64I2p0M2p0A2p0F2p0D2p0V1p0

C++ compilers will take this string as -march argument.
https://llvm.org/docs/RISCVUsage.html
https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html

[jdemel]

The GCC RISC-V architecture options imply that we could optimize for any given CPU. That'd be to many machines to compile, I assume.
The GCC argument would potentially be:

gcc -march=rv64i2p0m2p0a2p0f2p0d2p0v1p0

While I assume the clang argument is:

clang -march=rv64i2p0m2p0a2p0f2p0d2p0v1p0

I was hoping for smth like

gcc -march=rv64imafdv

I read that there are some names for a common set of extensions. This might be interesting as a baseline as well.

[drom]

You are right. The are some baselines like rv64g
also there are profiles https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
but for this project, I think important baseline is:

• rv64i - 64-bit
• f - float32
• d - float64
• v - vector (due to complications of Vector extension story I would explicitly say v1p0)
• m,a,c - (optional) most cores with come with Integer mul/div; atomics; compact instructions

[drom]

Another related question is: Are we using ASM or Intrinsics ?
Recently I switched to RVV intrinsics https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc
They are very handy and quite stable at this point.

[jdemel]

I suggest to use intrinsics. So far, we mostly use intrinsics and only rarely use ASM. Also, we tend to replace the ASM code with intrinsics when they're available.

If a platform comes with Vector extensions, is it reasonable to assume it comes with m,a,c too? If we decide to make this optional, we will eventually see situations where we have to work around this assumption. I'd like to keep things simple.

Would you be willing to set up an initial environment? I'd envision 2 options:

1. a generic machine for riscv64 that includes the sifive74 kernels.
2. a rv64imafdv1p0 machine

Currently, we use: https://github.com/uraimo/run-on-arch-action#supported-platforms for non-x86 platforms. If we can integrate a CI test for these machines, that'd be worthwhile.

As soon as we set up the initial machines and CI, we can start to add optimized kernels. It'd be interesting to see how well a compiler optimizes code compared to hand-optimized kernels.

[drom]

I can setup CI for:

1. HiFive Unmatched dev-board: https://www.sifive.com/boards/hifive-unmatched-revb
   u74 core. rv64imafdc
   Good in-order superscalar baseline. I have physical dev. board

2. https://www.sifive.com/cores/intelligence-x280
   Popular vector + in-order superscalar target.
   x280: rv64imafdcv1p0
   We can run on QEMU (What version of QEMU you use?)

I can setup cycle-accurate model benchmarking ~100KHz simulation speed.

[drmpeg]

Just an update. A board with a RVV 1.0 capable CPU has been released. The Banana Pi BPI-F3.

https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3

Current boards only have 4GB of RAM, so it may be better to wait for 8 or 16GB models to come out.