x86: add SHA-512 instructions to all-dec-instructions.txt

Unclear if this is the "correct" way to go about this. XED taken from https://github.com/intelxed/xed/blob/main/datafiles/sha512/sha512-isa.xed.txt. Change-Id: If5d7026f3020698727964e9838a6dff1653c846f Reviewed-on: https://go-review.googlesource.com/c/arch/+/645035 Reviewed-by: Cherry Mui <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]>
golang · Jan 28, 2025 · fa46516 · fa46516
1 parent ccff9d4
commit fa46516
Showing 1 changed file with 76 additions and 0 deletions.
diff --git a/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt b/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt
@@ -58027,3 +58027,79 @@ PATTERN   : 0x0F 0xAE MOD[mm]   MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no6
 OPERANDS  : MEM0:r:y
 
 }
+
+
+
+
+###FILE: ./datafiles/sha512/sha512-isa.xed.txt
+
+#BEGIN_LEGAL
+#
+#Copyright (c) 2023 Intel Corporation
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#  
+#END_LEGAL
+#
+#
+#
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#    ***** GENERATED FILE -- DO NOT EDIT! *****
+#
+#
+#
+AVX_INSTRUCTIONS()::
+# EMITTING VSHA512MSG1 (VSHA512MSG1-256-1)
+{
+ICLASS:      VSHA512MSG1
+CPL:         3
+CATEGORY:    SHA512
+EXTENSION:   SHA512
+ISA_SET:     SHA512
+EXCEPTIONS:  avx-type-6
+REAL_OPCODE: Y
+PATTERN:     VV1 0xCC VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR
+OPERANDS:    REG0=YMM_R():rw:qq:u64 REG1=XMM_B():r:dq:u64
+IFORM:       VSHA512MSG1_YMMu64_XMMu64
+}
+
+
+# EMITTING VSHA512MSG2 (VSHA512MSG2-256-1)
+{
+ICLASS:      VSHA512MSG2
+CPL:         3
+CATEGORY:    SHA512
+EXTENSION:   SHA512
+ISA_SET:     SHA512
+EXCEPTIONS:  avx-type-6
+REAL_OPCODE: Y
+PATTERN:     VV1 0xCD VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR
+OPERANDS:    REG0=YMM_R():rw:qq:u64 REG1=YMM_B():r:qq:u64
+IFORM:       VSHA512MSG2_YMMu64_YMMu64
+}
+
+
+# EMITTING VSHA512RNDS2 (VSHA512RNDS2-256-1)
+{
+ICLASS:      VSHA512RNDS2
+CPL:         3
+CATEGORY:    SHA512
+EXTENSION:   SHA512
+ISA_SET:     SHA512
+EXCEPTIONS:  avx-type-6
+REAL_OPCODE: Y
+PATTERN:     VV1 0xCB VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
+OPERANDS:    REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:dq:u64
+IFORM:       VSHA512RNDS2_YMMu64_YMMu64_XMMu64
+}