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NVMe-oF for Windows.

C 10 Updated Feb 4, 2023

Public repository of the data, scripts and methodology presented in the paper "Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface"

VHDL 10 3 Updated Apr 12, 2023

Two RX-channel 6 GHz FMCW radar design files

VHDL 251 92 Updated May 5, 2023
VHDL 27 13 Updated Feb 21, 2024

分享免费梯子/科学上网/代理/shadowsocks(SS)/ShadowsocksR(SSR)/V2ray(vmess)代理,2小时更新一次,分享Clash代理订阅源和配置文件订阅链接。

2,402 459 Updated Apr 3, 2024

Seminal work on blockNDP largely developed @ Huawei Research

C 5 1 Updated Oct 17, 2021

xk265:HEVC/H.265 Video Encoder IP Core (RTL)

Verilog 245 79 Updated Apr 9, 2023

OpenTitan: Open source silicon root of trust

SystemVerilog 2,763 830 Updated Apr 3, 2025

The OpenPiton Platform

Assembly 683 231 Updated Mar 9, 2025

FPGA 2.0 to use with AEWE HW

VHDL 1 1 Updated Feb 4, 2019

This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.

Verilog 48 17 Updated Aug 29, 2020

Triple Modular Redundancy

Verilog 25 7 Updated Sep 4, 2019

The C++ class library that deals with the CCSDS packet format.

C++ 49 9 Updated Aug 13, 2016

Serial ATA Host Bus Adapter Core for Virtex 6

XSLT 2 2 Updated Jul 17, 2014

PandA-bambu public repository

C++ 263 50 Updated Apr 2, 2025

Turning .NET software into FPGA hardware for faster execution and lower power usage.

VHDL 309 34 Updated Mar 6, 2025

RISC-V ISA based 32-bit processor written in HLS

C 17 9 Updated Nov 7, 2019

An HLS-synthesizable Dynamic Memory Manager for FPGAs

C 10 2 Updated Feb 28, 2022

A Benchmark Suit for FPGA High-Level Synthesis

C 4 2 Updated Jul 5, 2014

lightweight open HLS for FPGA rapid prototyping

C++ 20 2 Updated Mar 22, 2018

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

Jupyter Notebook 234 79 Updated Apr 12, 2021

Open Source CANopen Stack

C 60 38 Updated Oct 23, 2019

TCP-like protocol over a laser-communication system, implemented on an FPGA

SystemVerilog 6 6 Updated Jan 25, 2017

DCC protocol

VHDL 1 1 Updated Nov 18, 2018

FPGA-based Ethernet Transmitter-Receiver using various levels and protocols (MAC, IP, UDP)

1 1 Updated Nov 24, 2015

Streaming FPGA/ASIC code generator for Google Protocol Buffers.

Verilog 16 2 Updated Jan 29, 2021

Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces

Verilog 32 6 Updated Nov 29, 2024

A Real-time Inter-Process Communication (IPC) mechanism and library

C 28 9 Updated Mar 15, 2021

CDBUS Resource List

53 12 Updated Sep 20, 2024
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