[VPTO] Materialize VMOV copies for tied operands

[yexiaosu]

Motivation

Some A5 vector instructions use two-address semantics: one input must share the destination physical register and is overwritten by the result.

When multiple destructive instructions consume the same tied operand, Bisheng inserts additional VMOV instructions during later lowering. The current PTOAS scheduler works on VPTO IR and cannot see these backend-generated instructions, so its DAG, resource usage, latency, and register-pressure view are incomplete.

This change makes those physical copies explicit in VPTO IR before scheduling. It addresses the issue described in #1327.

Changes

• Add an unmasked, full-register pto.vmov operation.

  • The input and result must have identical single-register !pto.vreg types.
  • The operation is intentionally not Pure, preventing canonicalize, CSE, and DCE from removing or merging physical copies.
  • It is modeled as a schedulable PIPE_V operation without ordinary memory access.

• Add VPTOTiedOperandOpInterface to describe operand/result physical-register constraints.

• Register tied operands for:

  • pto.vmula: operand 0
  • pto.vmadd: operand 0
  • pto.vaxpy: operand 1
  • pto.chistv2: operand 0
  • pto.dhistv2: operand 0
  • pto.vusqz: operand 0

• Add scheduler-independent physical-register view-root helpers for pto.vbitcast and pto.pbitcast.

• Add the A5-only pto-vpto-materialize-tied-operand-copies pass.

  • For N destructive uses of the same physical root, the final safe material use owns the original register and the other uses receive N - 1 VMOV copies.
  • If a later ordinary read, cross-block use, or live-out use exists, all destructive uses receive copies.
  • Handwritten VMOV results form independent physical roots.
  • The pass is idempotent.

• Add legacy and CANN 9.0.0 LLVM emitter lowering:

  • llvm.hivm.vmov.v<lanes><type>
  • llvm.hivm.vmov.x.v<lanes><type>

• Add the design document and update the VPTO micro-ISA documentation.

Scope

The pass is registered for independent use through pto-test-opt, but is not added to the default ptoas pipeline in this change.

This PR does not modify scheduler selection strategies, DAG owner anti-dependencies, register-pressure tracking, or existing pass ordering. Those changes remain part of the scheduler integration follow-up.

Testing

• Added 7 VPTO lit tests covering:

  • tied-op coverage and operand indices
  • N - 1 materialization
  • conservative all-copy behavior
  • physical view chains
  • handwritten VMOV roots
  • pass idempotence
  • CSE/DCE preservation
  • target diagnostics
  • scheduling classification
  • both LLVM emitter variants

• Focused tests: 7 passed

• Full check-pto: 1850 passed, 1 unsupported, 0 failed

• Compliance check: 0 errors, 0 warnings