Refactor: merge the hbg task table into one ChipTaskStorage array - #2073
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📝 WalkthroughWalkthroughThe runtime consolidates task descriptors, payloads, and slot states into ChangesChip task storage consolidation
Estimated code review effort: 4 (Complex) | ~45 minutes Merge Risk: 🟠 High · up to The refactor changes shared task storage and scheduler addressing, but the current head still has a task-addressing mismatch that can read the wrong records and dependency validation that can create waits on unsubmitted tasks, potentially causing incorrect execution or non-termination; a stale adapter may also fail compilation when used. These concrete correctness issues should be fixed before merging. Poem
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✅ Passed checks (4 passed)
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In `@src/a5/runtime/host_build_graph/runtime/scheduler/scheduler_graph.h`:
- Line 28: Update the scheduler graph addressing helpers and view contract to
use ChipTaskStorage’s 320-byte record stride, with TaskDescriptor at offset 0
and TaskPayload at offset 128, replacing the separate 64-byte descriptor and
192-byte payload strides. Ensure addressing remains correct for multiple tasks,
and add coverage using at least two in-graph tasks.
In `@src/common/host_build_graph/shared/orchestrator.cpp`:
- Around line 1318-1321: Update append_fanin_or_fail() to reject explicit GLOBAL
dependencies whose referenced slot is in range but unallocated, before writing
fanin_slots or updating last_consumer_local_id. Preserve valid allocated GLOBAL
dependencies and existing local dependency handling.
In `@src/common/platform/include/aicpu/args_dump_aicpu.h`:
- Around line 286-290: Fix the stale forwarding overload for
dump_running_task_outputs so it no longer passes six arguments to the
four-argument overload; either construct and forward the required dump_one
callback or remove the adapter when unused, while preserving valid callers.
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📒 Files selected for processing (39)
src/a2a3/runtime/host_build_graph/aicpu/aicpu_executor.cppsrc/a2a3/runtime/host_build_graph/host/runtime_maker.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler.hsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_completion.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_completion.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/host_build_graph/aicpu/aicpu_executor.cppsrc/a5/runtime/host_build_graph/host/runtime_maker.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_completion.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_graph.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_completion.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/common/host_build_graph/device/graph_execution.cppsrc/common/host_build_graph/docs/GRAPH_EXECUTION.mdsrc/common/host_build_graph/graph_execution.hsrc/common/host_build_graph/runtime.hsrc/common/host_build_graph/runtime_types.hsrc/common/host_build_graph/self_relative_ptr.hsrc/common/host_build_graph/shared/orchestrator.cppsrc/common/host_build_graph/shared/runtime.cppsrc/common/host_build_graph/shared/runtime_core.cppsrc/common/host_build_graph/shared/shared_memory.cppsrc/common/host_build_graph/shared_memory.hsrc/common/platform/include/aicpu/args_dump_aicpu.htests/ut/cpp/a2a3/test_graph_activation.cpptests/ut/cpp/a2a3/test_hbg_submit_poison.cpptests/ut/cpp/a5/test_graph_activation.cpptests/ut/cpp/a5/test_hbg_submit_poison.cpptests/ut/cpp/common/test_hbg_graph_cache.cpptests/ut/cpp/common/test_hbg_graph_submit_failure.cpptests/ut/cpp/common/test_hbg_self_relative_ptr.cpptests/ut/cpp/common/test_hbg_sm_compaction.cpp
💤 Files with no reviewable changes (3)
- src/common/host_build_graph/shared/runtime.cpp
- src/a2a3/runtime/host_build_graph/aicpu/aicpu_executor.cpp
- src/a5/runtime/host_build_graph/aicpu/aicpu_executor.cpp
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A task's descriptor, slot state and payload were three shared-memory segments indexed in parallel, while an in-graph task already held the same three in one container. Both kinds of hbg task now live in a ChipTaskStorage, so their relative positions are that type's layout rather than data any of them stores. - The SM ships one storage segment instead of three, so the restack copies it once and no longer re-takes a slot's bindings: the change of pitch cannot move siblings apart when the distance is intra-type. - ChipTaskSlotState drops its payload/descriptor SelfRelativePtr pair and bind_buffers; each record reaches the other two through to_slot/to_descriptor/to_payload, one constant displacement each. The freed 16 bytes stay reserved so the record keeps its cache line. - TaskDescriptor is padded to the 64-byte line the storage places the slot state on. That padding already existed inside the container, so an in-graph task is unchanged at 320 bytes; a GLOBAL task's SM entry grows 296 -> 320. Its packed_buffer_base offset is unchanged, which is what AICore reads. - The A5 AICore graph view resolved a descriptor and a payload from two bases at their own strides, which held only while the three records were parallel arrays. Both now come from the storage array: one base, one 320-byte stride, a fixed offset per record. The view keeps its size, so the second address becomes reserved rather than shifting the layout. scheduler.h sees both the constants and the types, so it static_asserts one against the other in every AICPU TU that builds the A5 scheduler; the contract UT checks the same pairing at run time. - Binding checks go with the bindings. A slot's descriptor is always present now, so every null screen is unreachable. The one in append_fanin_or_fail was also the only thing rejecting a producer id this run never submitted, so that job is kept explicitly: the local id is bound against active_count(), which get_slot_state_by_task_id does not do and the old form only approximated. - Runtime::slot_states_ptr_ named the segment that no longer exists and was only ever written null; removed. - args_dump_aicpu.h took a slot state and reached the records from it, which forced one member spelling on both runtimes. It now takes the records, and dump_running_task_outputs takes a per-slot callback, so each runtime keeps its own way of relating them. - Both A5 scheduler UT harnesses built two parallel arrays, modelling the layout this runtime no longer uses, which would have let the wire strides drift with nothing to catch it. They hold one storage array now, which also makes "no record is instantiated outside a ChipTaskStorage" true in-tree rather than only stated. - A contract test walks several tasks and checks both records of each against the entry they belong to. The reverse lookup above it only proves the wire constants carry the right values; a helper striding by the wrong one agrees at task 0 and diverges after, which is exactly how the two-base form went unnoticed.
What
A task's descriptor, slot state and payload were three shared-memory segments
indexed in parallel, while an in-graph task already held the same three in one
container. Both kinds of hbg task now live in a
ChipTaskStorage, so theirrelative positions are that type's layout rather than data any of them stores.
completion_flagsdeliberately stays its own dense byte array: a fanin scanreads many producers' flags at once, which one cache line answers there and
would take one line per producer inside the 320-byte storage stride.
Why it is correct
compact_live_imagechanged the pitch between the mirror and the shipped image, so a slot's
delta to its payload had to be re-derived. Inside one
ChipTaskStoragethatdistance is the type's layout, so it survives the change of pitch and the
three segment copies collapse into one.
present now, so every
task == nullptrscreen is unreachable. Where such ascreen was also doing a second job, that job is kept explicitly: the one in
append_fanin_or_failwas the only thing rejecting a producer id this runnever submitted, so it is now a bound against
active_count()— the oldform only approximated it, and
get_slot_state_by_task_iddoes notbounds-check.
descriptor and a payload from two bases at their own strides, which only
held while the three records were parallel arrays. Both now come from the
storage array — one base, one 320-byte stride, a fixed offset per record.
args_dump_aicpu.hno longer forces one member spelling on bothruntimes. It took a slot state and reached the records from it, which only
worked while
tensormap_and_ringbufferandhost_build_graphspelled thatrelation identically. It now takes the records;
dump_running_task_outputstakes a per-slot callback.
tensormap_and_ringbuffer's data structures areuntouched — only its six call sites pass
*slot.task/*slot.payloadexplicitly.
Cost
TaskDescriptoris padded to the 64-byte line the storage places the slotstate on.
offsetof(packed_buffer_base)is unchanged, which is what AICorereads, but the size is not free everywhere:
Also worth knowing:
TaskDescriptor::reserved[24]andChipTaskSlotState::reserved[16]are never written, and the SM mirror is notzero-filled (init-on-write), so 40 bytes per task of uninitialized host memory
travel to the device. Functionally inert — nothing reads them — but it would
show up in any future hash or byte-compare of the image.
Layout guarantees
Three asserts hold the invariant the sibling accessors rest on:
to_slot/to_descriptor/to_payload(all six directions, const andnon-const) are each one function-local
constexprdisplacement. None of thethree types may be instantiated outside a
ChipTaskStorage— the UTs thatheld bare records were changed to hold whole entries, so that invariant is
true in-tree rather than merely stated.
The A5 wire constants stay literals because the AICore
.ocannot includeruntime_types.h.test_hbg_scheduler_contractsreverse-looks-up all threethrough
offsetof, where the types are visible, so a layout change fails thebuild instead of silently mis-addressing.
Testing
Verified on this branch with #2074 applied on top, since that fix is what makes
test_hbg_submit_poisoncompile at all (see below). All judged by exit code.a5sima2a3simST sim needs an explicit device pool (
--device 0-3); some L3 cases declaredevice_count=2and the default pool holds one.Depends on #2074
test_hbg_submit_poisondoes not compile onmain:tests/ut/cpp/a2a3/test_hbg_submit_poison.cpp:196,198,218,220useorch.fataland
header->orch_error_code, both retired by #2068, in two tests added by#2063. The two changes touch different regions of the file, so git merged them
without a conflict and the disagreement only surfaces at compile time.
The failing region is byte-identical between this branch and
upstream/main,and this branch does not touch
tests/ut/cpp/CMakeLists.txt. #2074 fixes it infour lines; this PR rebases cleanly once that lands.