[GSoC] Updated DC-DC Verilog Generation and Simulations by harshkhandeparkar · Pull Request #230 · idea-fasoc/OpenFASOC

harshkhandeparkar · 2023-08-23T17:05:33Z

Related to #211

Changes

Updated DC-DC Verilog generation to use the common Python module.
Used Mako syntax for the Verilog templates.
Fixed and enabled sky130hs platform for the generator (synthesis only).
Fixed multiple errors in the custom-defined auxiliary cells' CDL.
Simulations
- Added a netlist extracted from the synthesized Verilog with power pins added.
- Used the common simulation Python module for running simulations.
- Added a testbench for the DC-DC simulations using the Mako templating syntax.
- Currently only runs simulations for the cases in which all configuration pins are high and the case in which all are low.
Removed and gitignored unused code or files.

msaligane · 2023-10-23T15:25:28Z

@saicharan0112 @chetanyagoyal Have you had a chance to look into this?

saicharan0112 · 2023-11-03T10:18:36Z

sorry, I just saw this PR. I am not sure if I can check anything from the circuit point of view but the updates made to the scripts are pretty good and are aligning towards some kind of standard. I could add a check for this in my upcoming PR which is to address #245

openfasoc/generators/dcdc-gen/src/DCDC_BUFFER.template.sv

openfasoc/generators/dcdc-gen/src/DCDC_NOV_CLKGEN.sv

minghunghw · 2023-11-09T16:57:54Z

openfasoc/generators/dcdc-gen/flow/Makefile

What is the reason for removing dependencies for macro placement?

Neither the macro placement nor the place_six_stage.py file were working. I believe the Python file is incomplete, and the macro placement has some outdated code and no longer works with the latest version of OpenROAD. I had removed them to test if the rest of the flow was working, but it was not. Should I revert these changes?

@minghungumich ?

@andylithia can you review this PR.

Can you revert the changes and submit an issue about the dependency issue you're seeing? I can try to fix it

openfasoc/generators/dcdc-gen/src/DCDC_BUFFER.sv

openfasoc/generators/dcdc-gen/src/DCDC_SIX_STAGES_CONV.v

openfasoc/generators/dcdc-gen/src/dcdcInst.v

openfasoc/generators/dcdc-gen/tools/dcdc_simulation.py

AL-255

Need an additional PR to fix the OpenROAD dependency issue

AL-255 · 2024-01-09T21:10:45Z

openfasoc/generators/dcdc-gen/flow/Makefile

Can you revert the changes and submit an issue about the dependency issue you're seeing? I can try to fix it

* imported and used the verilog-generation module in dcdc-gen.py * updated dcdc_netlist.py to return parameters instead of generating the netlist

…dc-gen

…pulation step

* LFSR module used in the noise injection module was missing

harshkhandeparkar mentioned this pull request Aug 23, 2023

[GSoC] Common Python API #211

Open

11 tasks

msaligane requested review from alibillalhammoud and saicharan0112 September 5, 2023 15:21

harshkhandeparkar force-pushed the dcdc-verilog-mako branch 2 times, most recently from 34d6d25 to d4f68a1 Compare September 11, 2023 15:48

harshkhandeparkar force-pushed the dcdc-verilog-mako branch from d4f68a1 to 169936c Compare September 30, 2023 08:20

harshkhandeparkar force-pushed the dcdc-verilog-mako branch from 169936c to 2005e22 Compare October 9, 2023 15:09

msaligane requested review from AL-255 and minghunghw and removed request for alibillalhammoud November 8, 2023 18:39

minghunghw suggested changes Nov 9, 2023

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AL-255 reviewed Jan 9, 2024

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harshkhandeparkar added 16 commits January 10, 2024 15:39

feat: use the new verilog generation module in dcdc-gen

3b22652

* imported and used the verilog-generation module in dcdc-gen.py * updated dcdc_netlist.py to return parameters instead of generating the netlist

fix: return stringified powmux_config

6a9b124

feat: update dcdc-gen verilog to use Mako syntax

fc8fca9

feat: gitignore generated verilog in dcdc-gen

5b89116

feat: remove unused code in dcdc_gen.py

8f7b28d

feat: added a command to make clean to remove generated verilog in dc…

2c18599

…dc-gen

fix: added missing semicolon in dcdc verilog

721dff6

fix: removed simulations from clean command

6318148

fix: renamed dcdc-gen module_name to prevent collision

2f87a09

fix<dcdc>: run make finish for synth and apr

f9adecc

fix<dcdc>: copy the correct files from flow/ to work/

12dde5b

feat: uncomment sky130hd_dcdc make command

3bcbc7b

feat<dcdc>: added error handling for flow steps

13db917

fix<dcdc>: added 2_1_floorplan.def as a prerequisite for the def mani…

af21bea

…pulation step

fix<dcdc>: disabled custom macro placement which was not working

276ca01

fix<dcdc>: disabled the noise injection module

de601d5

* LFSR module used in the noise injection module was missing

harshkhandeparkar added 14 commits January 10, 2024 15:39

fix<dcdc>: commented unused input

633203a

fix<dcdc>: updated design name for sky130hs

567747b

feat<dcdc>: enabled sky130hs commands in makefile

b90b19b

feat<dcdc>: enabled sky130hs

836b136

fix: added the correct width values in blocks/

2ac0630

fix: updated more width values

00df85a

fix: removed typo from auxcell.cdl

f7e765e

feat: added extracted dcdc netlist

91c291c

feat: added a dcdc simulation testbench

1638bcc

feat: added make command to run dcdc simulations

ceb1527

feat: gitignored dcdc simulations

07a978e

fix: removed unused code and comments in dcdc_gen.py

ca2b5ed

fix: removed unused imports in dcdc generator

b94e660

fix<dcdc>: fixed typo in make clean

49ef422

harshkhandeparkar force-pushed the dcdc-verilog-mako branch 2 times, most recently from 915013b to 536e135 Compare January 10, 2024 10:12

fix: uncommented flow parts in Makefile

6e04b0d

harshkhandeparkar force-pushed the dcdc-verilog-mako branch from 536e135 to 6e04b0d Compare January 10, 2024 10:23

harshkhandeparkar changed the title ~~[GSoC] Updated DC-DC Verilog Generation, Flow, and Simulations~~ [GSoC] Updated DC-DC Verilog Generation and Simulations Jan 12, 2024

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[GSoC] Updated DC-DC Verilog Generation and Simulations#230

[GSoC] Updated DC-DC Verilog Generation and Simulations#230
harshkhandeparkar wants to merge 31 commits intoidea-fasoc:mainfrom
harshkhandeparkar:dcdc-verilog-mako

harshkhandeparkar commented Aug 23, 2023 •

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harshkhandeparkar commented Aug 23, 2023 •

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