Chipathon2024 SystemsGenesys

[Lefteris-B]

No description provided.

[Lefteris-B]

Initial code upload for divide-by-two circuit

[chetanyagoyal]

can you please rename the PR and provide a description of the circuit along with the python code. Follow the PR guidelines as mentioned in the doc.

[Lefteris-B]

Changes done. Can you point to the document please?

[chetanyagoyal]

here is the link to the doc

[alibillalhammoud]

Hello @Lefteris-B thank you for the PR. Can you confirm that the design is passing DRC/LVS? Also, could you please include the design in an independent python file. You can still import and use the design in your notebook.

For example, you can create a new file called filename.py and copy just the code needed to create the cell in that python file. In the notebook you can import the cell in the notebook using from filename import nameofcellfunction

[Lefteris-B]

I will work on it this weekend. Thank you.

[Lefteris-B]

We separated the notebook functionality into separate files. Also fixed the collab file. Looking into DRC, LVS

[harshkhandeparkar]

It would be good to generate the spice netlist for this. Refer to

OpenFASOC/openfasoc/generators/glayout/glayout/flow/blocks/composite/opamp/opamp.py

Line 26 in e7f4611

def opamp_output_stage_netlist(pdk: MappedPDK, output_amp_fet_ref: ComponentReference, biasParams: list) -> Netlist:

[harshkhandeparkar]

You can generate the spice netlist for this once the latch netlist is generated. Refer to

OpenFASOC/openfasoc/generators/glayout/glayout/flow/blocks/composite/opamp/opamp.py

Line 26 in e7f4611

def opamp_output_stage_netlist(pdk: MappedPDK, output_amp_fet_ref: ComponentReference, biasParams: list) -> Netlist:

[harshkhandeparkar]

@Lefteris-B any update on this?

[Lefteris-B]

@harshkhandeparkar Allow me a few more days please.