Draft: Chipathon2024 Mahowald-ers Regulated Cascoded Current Mirror block by amisapta15 · Pull Request #349 · idea-fasoc/OpenFASOC

amisapta15 · 2024-11-15T13:57:49Z

Team Mahowald-ers: PR for adding Regulated Cascoded Current Mirror block. This block will add a Cascode regulator block from this team's other PR for enhanced voltage swing.

Ref: DOI: 10.1109/AE54730.2022.9920096

This is an initial Commit and a Circuit (with description) will be added. Details of the goal of this PR can be found in this Gslides link presented in 05.09.2024 meeting

Current Status: A simple Current Mirror template is added. LVS is failing with Final result: Top level cell failed pin matching. Further comments will be added soon.

…tive

amisapta15 · 2024-11-15T23:48:06Z

Current LVS result

Contents of circuit 1:  Circuit: 'CM'
Circuit CM contains 6 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:   6
Circuit contains 4 nets.
Contents of circuit 2:  Circuit: 'CM'
Circuit CM contains 2 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:   2
Circuit contains 3 nets.

Circuit was modified by parallel/series device merging.
New circuit summary:

Contents of circuit 1:  Circuit: 'CM'
Circuit CM contains 3 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:   3
Circuit contains 4 nets.
Contents of circuit 2:  Circuit: 'CM'
Circuit CM contains 2 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:   2
Circuit contains 3 nets.

Circuit 1 contains 3 devices, Circuit 2 contains 2 devices. *** MISMATCH ***
Circuit 1 contains 4 nets,    Circuit 2 contains 3 nets. *** MISMATCH ***


Final result: 
Netlists do not match.
Logging to file "/tmp/tmptmfe16ns/CM_lvs.rpt" disabled
LVS Done.


Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8         |Circuit 2: sky130_fd_pr__nfet_01v8         
-------------------------------------------|-------------------------------------------
1                                          |1                                          
2                                          |2                                          
3                                          |3                                          
4                                          |4                                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Class CM (0):  Merged 3 parallel devices.
Subcircuit summary:
Circuit 1: CM                              |Circuit 2: CM                              
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->3)             |sky130_fd_pr__nfet_01v8 (8->2) **Mismatch* 
Number of devices: 3 **Mismatch**          |Number of devices: 2 **Mismatch**          
Number of nets: 4 **Mismatch**             |Number of nets: 3 **Mismatch**             
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: CM                              |Circuit 2: CM                              

---------------------------------------------------------------------------------------
Net: VSS                                   |Net: VSS                                   
  sky130_fd_pr__nfet_01v8/(1|3) = 2        |  sky130_fd_pr__nfet_01v8/(1|3) = 2        
                                           |  sky130_fd_pr__nfet_01v8/4 = 2            
                                           |                                           
Net: a_n1570_n931#                         |(no matching net)                          
  sky130_fd_pr__nfet_01v8/4 = 3            |                                           
  sky130_fd_pr__nfet_01v8/(1|3) = 2        |                                           
  sky130_fd_pr__nfet_01v8/2 = 1            |                                           
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: CM                              |Circuit 2: CM                              

---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__nfet_01v8:3        |(no matching instance)                     
  (1,3) = (6,6)                            |                                           
  2 = 6                                    |                                           
  4 = 6                                    |                                           
                                           |                                           
---------------------------------------------------------------------------------------
Netlists do not match.

Subcircuit pins:
Circuit 1: CM                              |Circuit 2: CM                              
-------------------------------------------|-------------------------------------------
VSS                                        |VSS                                        
VCOPY                                      |VCOPY                                      
VREF                                       |VREF                                       
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes CM and CM are equivalent.

Final result: Netlists do not match.

amisapta15 · 2024-11-15T23:49:57Z

… the drains

amisapta15 · 2024-11-24T21:14:37Z

Updated the Layout and decreased LVS Errors. Current LVS produces the following Errors

The error now comes from the labels 'VCOPYandVREF`, which seem to be floating. Not Sure How to connect the metal2 layer, metal 2 pin and metal2 labels

`
Logging to file "/tmp/tmpi4zjwy4q/CM_lvs.rpt" enabled
Circuit sky130_fd_pr__nfet_01v8 contains no devices.

Contents of circuit 1: Circuit: 'CM'
Circuit CM contains 6 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 6
Circuit contains 3 nets, and 2 disconnected pins.
Contents of circuit 2: Circuit: 'CM'
Circuit CM contains 3 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 3
Circuit contains 3 nets.

Circuit was modified by parallel/series device merging.
New circuit summary:

Contents of circuit 1: Circuit: 'CM'
Circuit CM contains 3 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 3
Circuit contains 3 nets, and 2 disconnected pins.
Contents of circuit 2: Circuit: 'CM'
Circuit CM contains 3 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 3
Circuit contains 3 nets.

Circuit 1 contains 3 devices, Circuit 2 contains 3 devices.
Circuit 1 contains 3 nets, Circuit 2 contains 3 nets.

Final result:
Top level cell failed pin matching.

Logging to file "/tmp/tmpi4zjwy4q/CM_lvs.rpt" disabled
LVS Done.

Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Cell CM (0) disconnected node: VCOPY
Cell CM (0) disconnected node: VREF
Class CM (0): Merged 3 parallel devices.
Cell CM (0) disconnected node: VCOPY
Cell CM (0) disconnected node: VREF
Subcircuit summary:

Circuit 1: CM	Circuit 2: CM
sky130_fd_pr__nfet_01v8 (6->3)	sky130_fd_pr__nfet_01v8 (6->3)
Number of devices: 3	Number of devices: 3
Number of nets: 3	Number of nets: 3

Netlists match uniquely with port errors.

Subcircuit pins:

Circuit 1: CM	Circuit 2: CM
VSS	VSS
(no matching pin)	VREF
(no matching pin)	VCOPY
VCOPY	(no matching pin)
VREF	(no matching pin)

Cell pin lists for CM and CM altered to match.
Device classes CM and CM are equivalent.

Final result: Top level cell failed pin matching.

`

amisapta15 · 2024-11-27T20:26:26Z

Finally Cleared LVS. Improvement suggestions on the layout (along with further technical checks) will be greatly appreciated. Specially need help with moving the components around to become DRC clean.

DRC is still being checked. Next Goal is to get the Spice SIm going to extract the IV curve of this CM

amisapta15 · 2024-11-27T20:27:21Z

current layout

amisapta15 · 2024-12-05T17:29:47Z

Schematic-wise, getting suggestions on the schematic code for these would be super helpful. Thanks in advance.

(a) I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code.

(b) We want to move the Vref pin and track to the other position. Not sure what port to use for that move.

(c) The positioning of the pins (Vref, Vopy, and Vss) isn't good. They don't produce errors but would be great to bring them outside the well and make their location aligned and parametrized proper way.

hope I am able to explain it in an understandable fashion.

...ut/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/CM_primitive_cell_test.py

...flow/blocks/composite/regulated_cascoded_current_mirror/regulated_cascoded_current_mirror.py

harshkhandeparkar · 2025-01-21T09:29:48Z

@amisapta15 any update on this?

amisapta15 · 2025-01-21T12:01:20Z

Hello! Thanks for the comments and sorry for the delay. I should be able to push an update by the weekend. Thanks

…` in regulated_cascoded_current_mirror.py The main component name was generic. It is updated as per the suggestion provided by the maintainer.

amisapta15 · 2025-01-29T05:15:48Z

@harshkhandeparkar Kindly see my responses in your comments. Also, please see my request for help in placing the nodes

Schematic-wise, getting suggestions on the schematic code for these would be super helpful. Thanks in advance.

(a) I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code.

(b) We want to move the Vref pin and track to the other position. Not sure what port to use for that move.

(c) The positioning of the pins (Vref, Vopy, and Vss) isn't good. They don't produce errors but would be great to bring them outside the well and make their location aligned and parametrized proper way.

hope I am able to explain it in an understandable fashion.

Please note aside from this, following Mehedi's comment (from back before Holidays) a new code will be pushed for a non-uniform current mirror component generation code, utilising the two_transistor_place and common_centroid_ab_ba.py and four_trasistors_interdigitized function will be pushed.

harshkhandeparkar · 2025-02-06T14:11:51Z

@harshkhandeparkar Kindly see my responses in your comments.

I can't see any replies to my comments. Did you reply on a different platform?

Schematic-wise, getting suggestions on the schematic code for these would be super helpful. Thanks in advance.

(a) I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code.

Can you send the gds for this? Also, can you highlight(or tell line nos) this part of your code?

(b) We want to move the Vref pin and track to the other position. Not sure what port to use for that move.

Which other position?

amisapta15 · 2025-02-06T18:35:29Z

...flow/blocks/composite/regulated_cascoded_current_mirror/regulated_cascoded_current_mirror.py

+                                       dummy=with_dummy,with_substrate_tap=with_substrate_tap,with_tie=with_tie,tie_layers=tie_layers)
+    elif type.lower() =="nfet" or type.lower() =="nmos":
+        currm= two_nfet_interdigitized(pdk,numcols=num_cols,width=Width,length=Length,fingers=fingers,dummy=with_dummy,
+                                       with_substrate_tap=with_substrate_tap,with_tie=with_tie,tie_layers=tie_layers)


I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code.

Has this been fixed now?

amisapta15 · 2025-02-06T18:37:04Z

openfasoc/generators/glayout/glayout/flow/pdk/sky130_mapped/sky130_mapped.py

+    "pad_label" : (76, 5),
+    "pwell_pin" : (122, 16),
+    "pwell_label" : (122, 5)
 }


This is the new addition to the pdk for making the labelling pdk agonastic. Not sure How to tell Glayout to use this file instead of what is installed in the miniconda folder

amisapta15 · 2025-02-06T18:37:13Z

@harshkhandeparkar Kindly see my responses in your comments.

I can't see any replies to my comments. Did you reply on a different platform?

I had commented on Github itself. There were some wrongly set settings. It should be visible to you now. Please let me know if it isn't.

Schematic-wise, getting suggestions on the schematic code for these would be super helpful. Thanks in advance.
(a) I'm not sure what's going on there. The Via from licon to met1 doesn't encompass the finger and the via to met 2 doesn't line up. The finger should be extended to fully enclose the via to met 1 track (blue), and the via between met1 and met2 (the red line) should be aligned with the previous via. I'm not sure how to achieve that in code.

Can you send the gds for this? Also, can you highlight(or tell line nos) this part of your code?

Yes and Yes. The GDS is added here

This particular problem comes directly from the two_n/pfet_interdigitized function. I have added a comment (with the question above) for that portion of the code. Hope that helps.

(b) We want to move the Vref pin and track to the other position. Not sure what port to use for that move.

Which other position?

Please see this earlier comment

or The following picture with red highlights!

msaligane · 2025-02-19T00:01:56Z

@alibillalhammoud Can you please take a look at this issue?

…amed

amisapta15 · 2025-02-23T12:08:22Z

Dear @harshkhandeparkar, both issues are opened in appropriate places, as we discussed in the comments.

A helper function is added and all unnecessary things have been shifted. Another GitHub action run will be very helpful.

New commit forward from this, add new regulated cascade blocks and begin prep for integration of the whole project (CM+regulated cascade) for tape-out. Please ignore all other files currently except the one we are discussing.

Kindly note the positioning issues with the pins aren't solved. But we can address this later when the whole block is integrated.

harshkhandeparkar · 2025-03-28T14:26:20Z

Dear @harshkhandeparkar, both issues are opened in appropriate places, as we discussed in the comments.

A helper function is added and all unnecessary things have been shifted. Another GitHub action run will be very helpful.

New commit forward from this, add new regulated cascade blocks and begin prep for integration of the whole project (CM+regulated cascade) for tape-out. Please ignore all other files currently except the one we are discussing.

Kindly note the positioning issues with the pins aren't solved. But we can address this later when the whole block is integrated.

@amisapta15 can you rebase your branch so the new workflow can run on this?
Edit: Once this is done, the new blocks can be easily added to the CI to run DRC and LVS on.

harshkhandeparkar · 2025-03-28T14:28:02Z

...t/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/current_mirror_WL_param.py

@@ -0,0 +1,126 @@
+import sys
+sys.path.append('../../elementary/current_mirror/')


Is this required?

harshkhandeparkar · 2025-03-28T14:29:01Z

...t/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/current_mirror_WL_param.py

+	return CMS.flatten()
+
+
+comp = current_mirror(sky130, numcols=2, device='nfet')


It would be better to add these commands to a function or under if __name__ == "__main__" so it doesn't accidentally run as a side-effect of importing the file.

harshkhandeparkar · 2025-03-28T14:29:26Z

...generators/glayout/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/helper.py

@@ -0,0 +1,17 @@
+from os import path, rename, environ , listdir, remove, chmod
+
+def delete_files_in_directory(directory_path):


Where is this used? Does os.rmtree not do the same?

harshkhandeparkar · 2025-03-28T14:30:00Z

...glayout/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/regulated_cascode.py

+	return reg_casc_netlist
+
+
+# def regulated_cascode_netlist(


If this code is unused, it would be better to delete it. If it is old code, it would remain in the git history.

harshkhandeparkar · 2025-03-28T14:31:46Z

...flow/blocks/composite/regulated_cascoded_current_mirror/regulated_cascoded_current_mirror.py

+print(netgen_lvs_result['result_str'])
+
+
+## Will be used in future for simulation


harshkhandeparkar · 2025-03-28T14:32:59Z

...blocks/composite/regulated_cascoded_current_mirror/self_regulated_cascoded_current_mirror.py

+
+from glayout.flow.pdk.util.comp_utils import prec_ref_center, prec_center, movey, evaluate_bbox, align_comp_to_port
+
+# def cascode_common_source_netlist(


harshkhandeparkar · 2025-03-28T14:35:38Z

...enerators/glayout/glayout/flow/blocks/composite/regulated_cascoded_current_mirror/GDS/CM.gds

It would be better to remove this file as it can be generated.

amisapta15 added 5 commits November 15, 2024 14:46

Added Basic blocks and Folders

28fce9b

added test code for the primitive cell

4164fc3

updated test code path for pulling current mirror template from primi…

52c5bc2

…tive

Added Labeling for ports

26afca6

Updated to reduce LVS errors

cb74ac2

added A pic of the layout

cda70f2

updated multipler in the Netlist

dffef6d

msaligane requested a review from alibillalhammoud November 20, 2024 00:05

amisapta15 added 19 commits November 24, 2024 21:22

Added delete files ina directory function

ab6bf6a

added route_quad from gdsfactory

1f574e0

added dummy line in Netlist generator

582d916

remove create via function

989293a

updated interdigitized structure arguments and inputs

3240e79

updated routing with manual functions

dd280bd

routed dummies to Welltie

1957e91

added wells

1871cc1

Adding ports to components

0469d82

tweaked netlist generator input in top component

af0b5e1

Updated label adding code for LVS checks

f3314f6

changed function calls for top level component

6777463

[Doesn't work yet] Metal 2 to Meta 3 via for connecting the labels to…

84481b3

… the drains

[Doesn;t work yet] added labels in metal 3

6350512

removed create via from init python funciton

00a02ea

removed and generated new gds

1289e87

shifted VREF and VCOPY labels

19dabb0

Latest GDS file uploaded

25f0aa9

added Pin definations for labels in sky130 mapped pdk

606834a

LVS cleared GDS uploaded

4229604

amisapta15 added 4 commits December 12, 2024 09:25

Cosmetic updates

57accdc

Updates for failed attempt to align the ports

902968f

both n/p fets work and pass DRC-LVS

49c0b67

Preparing pictures for presentation

1dcb1d8

harshkhandeparkar reviewed Dec 12, 2024

View reviewed changes

Updated the name of the component function to `cascode_current_mirror…

44738ca

…` in regulated_cascoded_current_mirror.py The main component name was generic. It is updated as per the suggestion provided by the maintainer.

amisapta15 commented Feb 6, 2025

View reviewed changes

msaligane requested a review from harshkhandeparkar February 13, 2025 16:33

added cascode blocks

7b89991

This was referenced Feb 23, 2025

fet placement utilities such as two_n/pfet_interdigitized Primitive block donot return a Netlist #364

Open

Addtion of metal_pin and metal_label layer definations in the mapped_py class #365

Closed

amisapta15 added 2 commits February 23, 2025 12:54

custom layer definations in mapped pdk is removed. Some files are ren…

fdc041a

…amed

helper file added for delete_directory function

11340c3

harshkhandeparkar reviewed Mar 28, 2025

View reviewed changes

amisapta15 added 3 commits April 12, 2025 10:50

Merge branch 'idea-fasoc:main' into main

743b979

Newly devloped blocks

6179bb6

remove un-necessary files

5c8bbdb

		@@ -0,0 +1,126 @@
		import sys
		sys.path.append('../../elementary/current_mirror/')

		return CMS.flatten()


		comp = current_mirror(sky130, numcols=2, device='nfet')

		@@ -0,0 +1,17 @@
		from os import path, rename, environ , listdir, remove, chmod

		def delete_files_in_directory(directory_path):

		print(netgen_lvs_result['result_str'])


		## Will be used in future for simulation


		from glayout.flow.pdk.util.comp_utils import prec_ref_center, prec_center, movey, evaluate_bbox, align_comp_to_port

		# def cascode_common_source_netlist(

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amisapta15 commented Nov 15, 2024

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amisapta15 commented Nov 27, 2024 •

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