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@marjevan marjevan released this 04 Mar 09:19
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v2025.03.02
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The release updates XED according to Intel's latest ISA publications, including AVX10.2 (Revision 3.0) and APX (Revision 6.0) architecture specifications.
This release also introduces major enhancements to the decoder control APIs.

ISA Updates

  • Added new APX instructions that promote the Diamond Rapids ISA.
  • Added support for AVX10.2 mnemonic renames.
  • Improved definitions for Intel SDM-recommended multi-byte NOPs (See #340).
  • Fixed ISA-SET discrepancy for FISTTP.
  • Corrected element types for VCVTQQ2PD and VGET{MANT,EXP}PBF16 instructions.
  • Refined TSX ISA definition for accurate disassembly representation.
  • Dropped compatibility mode SYSCALL per Intel's latest FRED specification.
  • Added missing PROTECTED_MODE and NOP XED attributes for existing ISA.

General

  • Python APIs: The _py binding APIs are now autogenerated during the build for an accurate representation of the chosen build kit.
    For more information, check the xed\pyext\examples\README.md file.
  • Python APIs example: Enhancements for the CFFI example and provided XedPy class.
  • Updated the XED build to support Clang versions 17 and 18.
  • Improved XED examples documentation and source-code comments.
  • Simplified the encode request for AVX10/256VL Embedded Rounding Control instructions by setting only the ROUNDC XED operand.

Fixes

  • Fixed UBSan errors (closes #339).
  • Fixed Sierra-Forest and other chip-excluded builds using the --no-{chip} build knobs (fixes #343).
  • Corrected SIB segment mapping for the R21 register (fixes #340).
  • Internal improvements and code cleanup (fixes #340).

Decoder

  • Added REAL-mode legality checks (INVALID_MODE error for illegal instructions).
  • Disassembler: Added support for Intel's recommended APX assembly syntax for NF (No Flags) and DFV (Default Flags Values) instructions.
  • Enhanced APIs for APX/DFV instructions to ensure simplicity and efficiency. See the API reference page and the xed-ex1.c example for more details.

API Improvements for Decoder ISA Control

The XED decoder control APIs now fully support the xed_chip_features_t structure, offering greater flexibility and control compared to the
xed_chip_enum_t concept, enabling users to customize feature sets with precision.

  • Improved the xed_chip_features_t APIs to provide fine-grained control over ISA initialization.
    This approach is now recommended over the raw xed3_operand_set_* APIs.
  • Introduced a new API, xed_set_decoder_modes(), which allows explicit initialization of decoder modes with improved performance through one-time decoder ISA initialization.

Backward Compatibility

  • Backward compatibility for existing APIs is maintained.
  • Backward compatibility for decoder initialization of several ISA features has been deprecated.
    Previously default-on features like P4 (PAUSE), LZCNT (replacing BSR), and TZCNT (replacing BSF) are now disabled by default unless explicitly enabled by users through the raw XED setter APIs or the chip/chip-features APIs.

Decoder PREFETCH as NOP - New Capability

  • Based on decoder ISA initialization, the XED decoder now returns NOPs instead of PREFETCH instructions when PREFETCH is not supported by the chip/features. Previously, PREFETCH instructions were returned as illegal if they were unsupported by the XED chip.

Usage Example

  • For detailed usage guidance, refer to the XED xed-ex4.c example tool, which includes decoder initialization recommendations for dual-encoding ISA.

Full Changelog: v2024.11.04...v2025.03.02

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