Disable support for CNL by default

NEWS

@@ -10,6 +10,12 @@ Version 2.4.5 - XX.XX.XXXX (IRQL fork)
     these formats, meaning that a workaround is needed for Chromium.
 
 * Don't advertise VAProfileHEVCMain10 format support on HSW and IVB.
+* Disabled Gen 10 (Cannon Lake) support by default.
+
+    The graphics hardware was never released and all support
+    for it in Mesa and Linux was removed between 2020 and 2021.
+
+    A build time option remains if someone for some reason needs it.
 
 Version 2.4.4 - 06.Apr.2025 (IRQL fork)
 

configure.ac

@@ -57,6 +57,11 @@ AC_ARG_ENABLE([wayland],
                     [build with VA/Wayland API support @<:@default=yes@:>@])],
     [], [enable_wayland="yes"])
 
+AC_ARG_ENABLE([gen10-support],
+    [AC_HELP_STRING([--enable-gen10-support],
+                    [build with support for unreleased Cannon Lake hardware @<:@default=no@:>@])],
+    [], [enable_gen10_support="no"])
+
 AC_ARG_ENABLE([hybrid-codec],
     [AC_HELP_STRING([--enable-hybrid-codec],
                     [build with hybrid codec support @<:@default=no@:>@])],
@@ -131,6 +136,11 @@ if test "$enable_hybrid_codec" = "yes"; then
     AC_DEFINE([HAVE_HYBRID_CODEC], [1], [Defined to 1 if hybrid codec is needed])
 fi
 
+if test "$enable_gen10_support" = "yes"; then
+    AC_DEFINE([ENABLE_GEN10_SUPPORT], [1], [Defined to 1 if Cannon Lake ES support is needed])
+fi
+
+AM_CONDITIONAL(USE_GEN10_SUPPORT, test "$enable_gen10_support" = "yes")
 AM_CONDITIONAL(ENABLE_TESTS, test "$enable_tests" = "yes")
 
 VA_VERSION=`$PKG_CONFIG --modversion libva`
@@ -222,5 +232,7 @@ echo
 echo VA-API version ................... : $VA_VERSION_STR
 echo VA-API drivers path .............. : $LIBVA_DRIVERS_PATH
 echo Windowing systems ................ : $BACKENDS
+echo CNL support ...................... : $enable_gen10_support
+echo Hybrid driver support ............ : $enable_hybrid_codec
 echo Build tests ...................... : $enable_tests
 echo

meson_options.txt

@@ -1,5 +1,8 @@
 option('driverdir', type : 'string', description : 'drivers path')
 option('with_x11', type : 'combo', choices : ['yes', 'no', 'auto'], value : 'auto')
 option('with_wayland', type : 'combo', choices : ['yes', 'no', 'auto'], value : 'auto')
-option('enable_hybrid_codec', type : 'boolean', value : false)
+option('enable_gen10_support', type : 'boolean', value : false,
+    description: 'Enables support for unreleased Cannon Lake (Gen10) iGPUs')
+option('enable_hybrid_codec', type : 'boolean', value : false,
+    description: 'Enables support for loading the seperate hybrid codec driver.')
 option('enable_tests', type : 'boolean', value : false)

src/Makefile.sources

@@ -65,14 +65,6 @@ source_c = \
 	gen9_hevc_enc_kernels_binary.c \
 	gen9_hevc_encoder.c \
 	gen9_hevc_enc_utils.c \
-	gen10_encoder_vp8.c \
-	gen10_hcp_common.c \
-	gen10_hevc_enc_kernels_binary.c \
-	gen10_hevc_enc_common.c \
-	gen10_hevc_encoder.c \
-	gen10_huc_common.c \
-	gen10_vdenc_common.c \
-	gen10_vdenc_vp9.c \
 	$(NULL)
 
 source_h = \
@@ -141,13 +133,27 @@ source_h = \
 	gen9_hevc_enc_kernels_binary.h \
 	gen9_hevc_enc_utils.h \
 	gen9_hevc_encoder.h \
-	gen10_hcp_common.h \
-	gen10_hevc_enc_kernel.h \
-	gen10_hevc_enc_kernels_binary.h \
-	gen10_hevc_enc_common.h \
-	gen10_hevc_encoder.h \
-	gen10_hevc_enc_const_def.h \
-	gen10_huc_common.h \
-	gen10_vdenc_common.h \
-	gen10_vdenc_vp9.h \
 	$(NULL)
+
+if USE_GEN10_SUPPORT
+source_c +=  \
+    gen10_encoder_vp8.c \
+    gen10_hcp_common.c \
+    gen10_hevc_enc_kernels_binary.c \
+    gen10_hevc_enc_common.c \
+    gen10_hevc_encoder.c \
+    gen10_huc_common.c \
+    gen10_vdenc_common.c \
+    gen10_vdenc_vp9.c
+
+source_h +=  \
+    gen10_hcp_common.h \
+    gen10_hevc_enc_kernel.h \
+    gen10_hevc_enc_kernels_binary.h \
+    gen10_hevc_enc_common.h \
+    gen10_hevc_encoder.h \
+    gen10_hevc_enc_const_def.h \
+    gen10_huc_common.h \
+    gen10_vdenc_common.h \
+    gen10_vdenc_vp9.h
+endif

src/gen75_picture_process.c

@@ -84,8 +84,10 @@ gen75_vpp_vebox(VADriverContextP ctx,
 		va_status = gen8_vebox_process_picture(ctx, proc_ctx->vpp_vebox_ctx);
 	else if (IS_GEN9(i965->intel.device_info))
 		va_status = gen9_vebox_process_picture(ctx, proc_ctx->vpp_vebox_ctx);
+#if defined(ENABLE_GEN10_SUPPORT)
 	else if (IS_GEN10(i965->intel.device_info))
 		va_status = gen10_vebox_process_picture(ctx, proc_ctx->vpp_vebox_ctx);
+#endif
 
 	return va_status;
 }

src/gen75_vpp_vebox.c

@@ -2474,6 +2474,7 @@ gen9_vebox_process_picture(VADriverContextP ctx,
 	return status;
 }
 
+#if defined(ENABLE_GEN10_SUPPORT)
 void
 cnl_veb_state_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx)
 {
@@ -2731,3 +2732,4 @@ gen10_vebox_process_picture(VADriverContextP ctx, struct intel_vebox_context *pr
 
 	return status;
 }
+#endif

src/gen8_mfc.c

@@ -735,6 +735,7 @@ gen8_mfc_pipe_buf_addr_state(VADriverContextP ctx,
 	ADVANCE_BCS_BATCH(batch);
 }
 
+#if defined(ENABLE_GEN10_SUPPORT)
 static void
 gen10_mfc_pipe_buf_addr_state(VADriverContextP ctx,
 							  struct intel_encoder_context *encoder_context)
@@ -846,6 +847,7 @@ gen10_mfc_pipe_buf_addr_state(VADriverContextP ctx,
 
 	ADVANCE_BCS_BATCH(batch);
 }
+#endif
 
 static void
 gen8_mfc_avc_directmode_state(VADriverContextP ctx,
@@ -4204,6 +4206,7 @@ gen8_mfc_vp8_bsp_buf_base_addr_state(VADriverContextP ctx,
 
 #define ENCODE_INPUT_SOURCE     4
 
+#if defined(ENABLE_GEN10_SUPPORT)
 static void
 gen10_vp8_mfc_input_surface(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 {
@@ -4232,6 +4235,7 @@ gen10_vp8_mfc_input_surface(VADriverContextP ctx, struct intel_encoder_context *
 
 	ADVANCE_BCS_BATCH(batch);
 }
+#endif
 
 static void
 gen8_mfc_vp8_pipeline_picture_programing(VADriverContextP ctx,
@@ -4244,14 +4248,18 @@ gen8_mfc_vp8_pipeline_picture_programing(VADriverContextP ctx,
 	mfc_context->pipe_mode_select(ctx, MFX_FORMAT_VP8, encoder_context);
 	mfc_context->set_surface_state(ctx, encoder_context);
 
+#if defined(ENABLE_GEN10_SUPPORT)
 	if (IS_GEN10(i965->intel.device_info))
 		gen10_vp8_mfc_input_surface(ctx, encoder_context);
+#endif
 
 	mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 
+#if defined(ENABLE_GEN10_SUPPORT)
 	if (IS_GEN10(i965->intel.device_info))
 		gen10_mfc_pipe_buf_addr_state(ctx, encoder_context);
 	else
+#endif
 		gen8_mfc_pipe_buf_addr_state(ctx, encoder_context);
 
 	gen8_mfc_bsp_buf_base_addr_state(ctx, encoder_context);

src/gen9_mfc.c

@@ -67,16 +67,20 @@ Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *e
 			return gen9_avc_pak_context_init(ctx, encoder_context);
 
 	case CODEC_HEVC:
+#if defined(ENABLE_GEN10_SUPPORT)
 		if (IS_GEN10(i965->intel.device_info))
 			return gen10_hevc_pak_context_init(ctx, encoder_context);
 		else
+#endif
 			return gen9_hevc_pak_context_init(ctx, encoder_context);
 
 	case CODEC_VP9:
+#if defined(ENABLE_GEN10_SUPPORT)
 		if (encoder_context->low_power_mode) {
 			assert(IS_GEN10(i965->intel.device_info));
 			return gen10_vdenc_vp9_context_init(ctx, encoder_context);
 		} else
+#endif
 			return gen9_vp9_pak_context_init(ctx, encoder_context);
 	}
 

src/gen9_mfd.c

@@ -220,9 +220,11 @@ gen9_hcpd_pipe_mode_select(VADriverContextP ctx,
 			OUT_BCS_BATCH(batch, 0);
 
 		OUT_BCS_BATCH(batch, 0);
+#if defined(ENABLE_GEN10_SUPPORT)
 	} else if (IS_GEN10(i965->intel.device_info)) {
 		OUT_BCS_BATCH(batch, 0);
 		OUT_BCS_BATCH(batch, 0);
+#endif
 	}
 
 	ADVANCE_BCS_BATCH(batch);
@@ -353,6 +355,7 @@ gen9_hcpd_ind_obj_base_addr_state(VADriverContextP ctx,
 	ADVANCE_BCS_BATCH(batch);
 }
 
+#if defined(ENABLE_GEN10_SUPPORT)
 static void
 gen10_hcpd_ind_obj_base_addr_state(VADriverContextP ctx,
 								   dri_bo *slice_data_bo,
@@ -413,6 +416,7 @@ gen10_hcpd_ind_obj_base_addr_state(VADriverContextP ctx,
 
 	ADVANCE_BCS_BATCH(batch);
 }
+#endif
 
 static void
 gen9_hcpd_qm_state(VADriverContextP ctx,
@@ -1008,9 +1012,11 @@ gen9_hcpd_hevc_decode_picture(VADriverContextP ctx,
 		slice_param = (VASliceParameterBufferHEVC *)decode_state->slice_params[j]->buffer;
 		slice_data_bo = decode_state->slice_datas[j]->bo;
 
+#if defined(ENABLE_GEN10_SUPPORT)
 		if (IS_GEN10(i965->intel.device_info))
 			gen10_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
 		else
+#endif
 			gen9_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
 
 		if (j == decode_state->num_slice_params - 1)
@@ -1822,9 +1828,11 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
 
 	gen9_hcpd_vp9_pipe_buf_addr_state(ctx, decode_state, gen9_hcpd_context);
 
+#if defined(ENABLE_GEN10_SUPPORT)
 	if (IS_GEN10(i965->intel.device_info))
 		gen10_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
 	else
+#endif
 		gen9_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
 
 	//If segmentation is disabled, only SegParam[0] is valid,

src/gen9_vme.c

@@ -1999,9 +1999,11 @@ Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e
 			   encoder_context->codec == CODEC_H264_MVC) {
 		return gen9_avc_vme_context_init(ctx, encoder_context);
 	} else if (encoder_context->codec == CODEC_HEVC) {
+#if defined(ENABLE_GEN10_SUPPORT)
 		if (IS_GEN10(i965->intel.device_info))
 			return gen10_hevc_vme_context_init(ctx, encoder_context);
 		else
+#endif
 			return gen9_hevc_vme_context_init(ctx, encoder_context);
 	}
 

src/i965_avc_encoder.c

@@ -9403,8 +9403,10 @@ gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_cont
 	int i;
 	unsigned int cmd_len = 65;
 
+#if defined(ENABLE_GEN10_SUPPORT)
 	if (IS_GEN10(i965->intel.device_info))
 		cmd_len = 68;
+#endif
 
 	BEGIN_BCS_BATCH(batch, cmd_len);
 
@@ -9451,12 +9453,14 @@ gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_cont
 	/* the DW 62-64 is the buffer */
 	OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
 
+#if defined(ENABLE_GEN10_SUPPORT)
 	/*65-67 for CNL */
 	if (IS_GEN10(i965->intel.device_info)) {
 		OUT_BCS_BATCH(batch, 0);
 		OUT_BCS_BATCH(batch, 0);
 		OUT_BCS_BATCH(batch, 0);
 	}
+#endif
 
 	ADVANCE_BCS_BATCH(batch);
 }
@@ -11165,11 +11169,14 @@ gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *en
 			   IS_GLK(i965->intel.device_info)) {
 		generic_ctx->enc_kernel_ptr = (void *)kbl_avc_encoder_kernels;
 		generic_ctx->enc_kernel_size = sizeof(kbl_avc_encoder_kernels);
+#if defined(ENABLE_GEN10_SUPPORT)
 	} else if (IS_GEN10(i965->intel.device_info)) {
 		generic_ctx->enc_kernel_ptr = (void *)cnl_avc_encoder_kernels;
 		generic_ctx->enc_kernel_size = sizeof(cnl_avc_encoder_kernels);
-	} else
+#endif
+	} else {
 		goto allocate_structure_failed;
+	}
 
 	/* initialize misc ? */
 	avc_ctx->ctx = ctx;
@@ -11385,8 +11392,10 @@ gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *en
 		avc_state->lambda_table_enable = 1;
 		avc_state->brc_split_enable = 1;
 
+#if defined(ENABLE_GEN10_SUPPORT)
 		if (IS_GEN10(i965->intel.device_info))
 			avc_state->adaptive_transform_decision_enable = 1;// CNL
+#endif
 	}
 
 	avc_state->num_refs[0] = 0;

src/i965_avc_encoder_kernels.c

@@ -41627,6 +41627,7 @@ const unsigned int bdw_avc_encoder_kernels[AVC_ENC_BDW_SZ] = {
 	0x00000000, 0x00000000, 0x00000000, 0x00000000
 };
 
+#if defined(ENABLE_GEN10_SUPPORT)
 const unsigned int cnl_avc_encoder_kernels[AVC_ENC_CNL_SZ] = {
 	0x0000001b, 0x00000088, 0x000013c8, 0x00008f88, 0x00012ec8, 0x00014208, 0x0001bdc8, 0x00025d08,
 	0x00027048, 0x0002b288, 0x00030fc8, 0x000323c8, 0x0003b788, 0x000456c8, 0x000466c8, 0x00048388,
@@ -54295,3 +54296,4 @@ const unsigned int cnl_avc_encoder_kernels[AVC_ENC_CNL_SZ] = {
 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000
 };
+#endif

src/i965_avc_encoder_kernels.h

@@ -42,7 +42,9 @@ extern const unsigned int kbl_avc_encoder_kernels[AVC_ENC_KBL_SZ];
 #define AVC_ENC_BDW_SZ 96428
 extern const unsigned int bdw_avc_encoder_kernels[AVC_ENC_BDW_SZ];
 
+#if defined(ENABLE_GEN10_SUPPORT)
 #define AVC_ENC_CNL_SZ 101330
 extern const unsigned int cnl_avc_encoder_kernels[AVC_ENC_CNL_SZ];
+#endif
 
 #endif//_I965_AVC_ENCODER_KERNELS_H

src/i965_device_info.c

@@ -779,6 +779,7 @@ static struct hw_codec_info cfl_hw_codec_info = {
 	},
 };
 
+#if defined(ENABLE_GEN10_SUPPORT)
 static struct hw_codec_info cnl_hw_codec_info = {
 	.dec_hw_context_init = gen9_dec_hw_context_init,
 	.enc_hw_context_init = gen9_enc_hw_context_init,
@@ -851,6 +852,7 @@ static struct hw_codec_info cnl_hw_codec_info = {
 		{VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
 	},
 };
+#endif
 
 struct hw_codec_info *
 i965_get_codec_info(int devid)
@@ -1030,12 +1032,14 @@ static const struct intel_device_info cfl_device_info = {
 	.is_cfllake = 1,
 };
 
+#if defined(ENABLE_GEN10_SUPPORT)
 static const struct intel_device_info cnl_device_info = {
 	.gen = 10,
 
 	.urb_size = 4096,
 	.max_wm_threads = 64,       /* per PSD */
 };
+#endif
 
 const struct intel_device_info *
 i965_get_device_info(int devid)

src/i965_encoder_api.h

@@ -52,10 +52,12 @@ gen9_hevc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *e
 extern Bool
 gen9_hevc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 
+#if defined(ENABLE_GEN10_SUPPORT)
 extern Bool
 gen10_hevc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
 
 extern Bool
 gen10_hevc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+#endif
 
 #endif  // _I965_ENCODER_API_H_