[PW_SID:1100569] [v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support#2013
[PW_SID:1100569] [v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support#2013linux-riscv-bot wants to merge 2 commits into
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ZICNTR allows the CPU time to be read using CSRs, which used to be the default. If ZICNTR is supported prefer using CSRs over MMIO. This may also be faster as CSRs are not emulated in M-mode. Signed-off-by: Jesse Taube <jtaubepe@redhat.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
To use the T-HEAD C9xx clint in RISCV-M NOMMU env, we need to take
care two points:
1.The mtimecmp in T-Head C9xx clint only supports 32bit read/write,
implement such support.
2. As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer:
add a quirk for lacking mtime register") of opensbi:
"T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continuous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR."
So, we need to fall back to read time CSR instead of mtime register
using RISCV_ISA_EXT_ZICNTR.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Jesse Taube <jtaubepe@redhat.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 1: "[v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
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Patch 2: "[v7,2/2] clocksource/drivers/timer-clint: Add T-Head C9xx clint" |
PR for series 1100569 applied to workflow__riscv__fixes
Name: [v7,1/2] clocksource/drivers/timer-clint: Add ZICNTR support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1100569
Version: 7