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RKSimonRKSimon
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[X86] Add tests showing failure to concat matching SITOFP/UITOFP vector ops (#172852)
Tests have to perform an additional FADD to prevent combineConcatVectorOfCasts from performing the fold - we're trying to show when this fails to occur during a combineConcatVectorOps recursion Interestingly, due to uitofp expansion AVX1/2 is often managing to concat where AVX512 can't
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‎llvm/test/CodeGen/X86/combine-sitofp.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
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define <4 x double> @concat_sitofp_v4f64_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x double> %b0, <2 x double> %b1) {
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; SSE-LABEL: concat_sitofp_v4f64_v2i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
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; SSE-NEXT: addpd %xmm2, %xmm0
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; SSE-NEXT: addpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: concat_sitofp_v4f64_v2i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm1, %xmm1
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; AVX-NEXT: vaddpd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vaddpd %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%c0 = sitofp <2 x i32> %a0 to <2 x double>
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%c1 = sitofp <2 x i32> %a1 to <2 x double>
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%v0 = fadd <2 x double> %b0, %c0
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%v1 = fadd <2 x double> %b1, %c1
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%res = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x double> %res
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}
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define <8 x float> @concat_sitofp_v8f32_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x float> %b0, <4 x float> %b1) {
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; SSE-LABEL: concat_sitofp_v8f32_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
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; SSE-NEXT: addps %xmm2, %xmm0
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; SSE-NEXT: addps %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: concat_sitofp_v8f32_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2ps %xmm1, %xmm1
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; AVX-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vaddps %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%c0 = sitofp <4 x i32> %a0 to <4 x float>
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%c1 = sitofp <4 x i32> %a1 to <4 x float>
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%v0 = fadd <4 x float> %b0, %c0
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%v1 = fadd <4 x float> %b1, %c1
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%res = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x float> %res
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}
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define <8 x double> @concat_sitofp_v8f64_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2, <2 x i32> %a3, <2 x double> %b0, <2 x double> %b1, <2 x double> %b2, <2 x double> %b3) {
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; SSE-LABEL: concat_sitofp_v8f64_v2i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
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; SSE-NEXT: cvtdq2pd %xmm2, %xmm2
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; SSE-NEXT: cvtdq2pd %xmm3, %xmm3
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; SSE-NEXT: addpd %xmm4, %xmm0
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; SSE-NEXT: addpd %xmm5, %xmm1
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; SSE-NEXT: addpd %xmm6, %xmm2
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; SSE-NEXT: addpd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1OR2-LABEL: concat_sitofp_v8f64_v2i32:
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; AVX1OR2: # %bb.0:
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; AVX1OR2-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX1OR2-NEXT: vcvtdq2pd %xmm1, %xmm1
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; AVX1OR2-NEXT: vcvtdq2pd %xmm2, %xmm2
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; AVX1OR2-NEXT: vcvtdq2pd %xmm3, %xmm3
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; AVX1OR2-NEXT: vaddpd %xmm0, %xmm4, %xmm0
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; AVX1OR2-NEXT: vaddpd %xmm1, %xmm5, %xmm1
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; AVX1OR2-NEXT: vaddpd %xmm2, %xmm6, %xmm2
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; AVX1OR2-NEXT: vaddpd %xmm3, %xmm7, %xmm3
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; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
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; AVX1OR2-NEXT: retq
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;
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; AVX512-LABEL: concat_sitofp_v8f64_v2i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX512-NEXT: vcvtdq2pd %xmm1, %xmm1
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; AVX512-NEXT: vcvtdq2pd %xmm2, %xmm2
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; AVX512-NEXT: vcvtdq2pd %xmm3, %xmm3
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; AVX512-NEXT: vaddpd %xmm0, %xmm4, %xmm0
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; AVX512-NEXT: vaddpd %xmm1, %xmm5, %xmm1
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; AVX512-NEXT: vaddpd %xmm2, %xmm6, %xmm2
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; AVX512-NEXT: vaddpd %xmm3, %xmm7, %xmm3
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; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
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; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
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; AVX512-NEXT: retq
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%c0 = sitofp <2 x i32> %a0 to <2 x double>
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%c1 = sitofp <2 x i32> %a1 to <2 x double>
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%c2 = sitofp <2 x i32> %a2 to <2 x double>
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%c3 = sitofp <2 x i32> %a3 to <2 x double>
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%v0 = fadd <2 x double> %b0, %c0
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%v1 = fadd <2 x double> %b1, %c1
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%v2 = fadd <2 x double> %b2, %c2
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%v3 = fadd <2 x double> %b3, %c3
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%r01 = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%r23 = shufflevector <2 x double> %v2, <2 x double> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%res = shufflevector <4 x double> %r01, <4 x double> %r23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x double> %res
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}
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define <16 x float> @concat_sitofp_v16f32_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3, <4 x float> %b0, <4 x float> %b1, <4 x float> %b2, <4 x float> %b3) {
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; SSE-LABEL: concat_sitofp_v16f32_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
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; SSE-NEXT: cvtdq2ps %xmm2, %xmm2
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; SSE-NEXT: cvtdq2ps %xmm3, %xmm3
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; SSE-NEXT: addps %xmm4, %xmm0
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; SSE-NEXT: addps %xmm5, %xmm1
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; SSE-NEXT: addps %xmm6, %xmm2
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; SSE-NEXT: addps %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1OR2-LABEL: concat_sitofp_v16f32_v4i32:
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; AVX1OR2: # %bb.0:
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; AVX1OR2-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX1OR2-NEXT: vcvtdq2ps %xmm1, %xmm1
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; AVX1OR2-NEXT: vcvtdq2ps %xmm2, %xmm2
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; AVX1OR2-NEXT: vcvtdq2ps %xmm3, %xmm3
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; AVX1OR2-NEXT: vaddps %xmm0, %xmm4, %xmm0
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; AVX1OR2-NEXT: vaddps %xmm1, %xmm5, %xmm1
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; AVX1OR2-NEXT: vaddps %xmm2, %xmm6, %xmm2
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; AVX1OR2-NEXT: vaddps %xmm3, %xmm7, %xmm3
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; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
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; AVX1OR2-NEXT: retq
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;
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; AVX512-LABEL: concat_sitofp_v16f32_v4i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX512-NEXT: vcvtdq2ps %xmm1, %xmm1
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; AVX512-NEXT: vcvtdq2ps %xmm2, %xmm2
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; AVX512-NEXT: vcvtdq2ps %xmm3, %xmm3
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; AVX512-NEXT: vaddps %xmm0, %xmm4, %xmm0
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; AVX512-NEXT: vaddps %xmm1, %xmm5, %xmm1
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; AVX512-NEXT: vaddps %xmm2, %xmm6, %xmm2
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; AVX512-NEXT: vaddps %xmm3, %xmm7, %xmm3
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; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
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; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
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; AVX512-NEXT: retq
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%c0 = sitofp <4 x i32> %a0 to <4 x float>
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%c1 = sitofp <4 x i32> %a1 to <4 x float>
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%c2 = sitofp <4 x i32> %a2 to <4 x float>
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%c3 = sitofp <4 x i32> %a3 to <4 x float>
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%v0 = fadd <4 x float> %b0, %c0
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%v1 = fadd <4 x float> %b1, %c1
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%v2 = fadd <4 x float> %b2, %c2
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%v3 = fadd <4 x float> %b3, %c3
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%r01 = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%r23 = shufflevector <4 x float> %v2, <4 x float> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%res = shufflevector <8 x float> %r01, <8 x float> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x float> %res
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}
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define <8 x double> @concat_sitofp_v8f64_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x double> %b0, <4 x double> %b1) {
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; SSE-LABEL: concat_sitofp_v8f64_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
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; SSE-NEXT: cvtdq2pd %xmm6, %xmm6
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm1[2,3,2,3]
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; SSE-NEXT: cvtdq2pd %xmm7, %xmm7
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; SSE-NEXT: cvtdq2pd %xmm1, %xmm8
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; SSE-NEXT: addpd %xmm2, %xmm0
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; SSE-NEXT: addpd %xmm3, %xmm6
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; SSE-NEXT: addpd %xmm4, %xmm8
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; SSE-NEXT: addpd %xmm5, %xmm7
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; SSE-NEXT: movapd %xmm6, %xmm1
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; SSE-NEXT: movapd %xmm8, %xmm2
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; SSE-NEXT: movapd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1OR2-LABEL: concat_sitofp_v8f64_v4i32:
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; AVX1OR2: # %bb.0:
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; AVX1OR2-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX1OR2-NEXT: vcvtdq2pd %xmm1, %ymm1
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; AVX1OR2-NEXT: vaddpd %ymm0, %ymm2, %ymm0
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; AVX1OR2-NEXT: vaddpd %ymm1, %ymm3, %ymm1
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; AVX1OR2-NEXT: retq
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;
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; AVX512-LABEL: concat_sitofp_v8f64_v4i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512-NEXT: vcvtdq2pd %xmm1, %ymm1
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; AVX512-NEXT: vaddpd %ymm0, %ymm2, %ymm0
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; AVX512-NEXT: vaddpd %ymm1, %ymm3, %ymm1
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; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512-NEXT: retq
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%c0 = sitofp <4 x i32> %a0 to <4 x double>
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%c1 = sitofp <4 x i32> %a1 to <4 x double>
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%v0 = fadd <4 x double> %b0, %c0
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%v1 = fadd <4 x double> %b1, %c1
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%res = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x double> %res
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}
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define <16 x float> @concat_sitofp_v16f32_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x float> %b0, <8 x float> %b1) {
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; SSE-LABEL: concat_sitofp_v16f32_v8i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: cvtdq2ps %xmm3, %xmm3
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; SSE-NEXT: cvtdq2ps %xmm2, %xmm2
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; SSE-NEXT: addps %xmm4, %xmm0
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; SSE-NEXT: addps %xmm5, %xmm1
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; SSE-NEXT: addps %xmm6, %xmm2
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; SSE-NEXT: addps %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1OR2-LABEL: concat_sitofp_v16f32_v8i32:
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; AVX1OR2: # %bb.0:
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; AVX1OR2-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX1OR2-NEXT: vcvtdq2ps %ymm1, %ymm1
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; AVX1OR2-NEXT: vaddps %ymm0, %ymm2, %ymm0
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; AVX1OR2-NEXT: vaddps %ymm1, %ymm3, %ymm1
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; AVX1OR2-NEXT: retq
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;
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; AVX512-LABEL: concat_sitofp_v16f32_v8i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX512-NEXT: vcvtdq2ps %ymm1, %ymm1
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; AVX512-NEXT: vaddps %ymm0, %ymm2, %ymm0
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; AVX512-NEXT: vaddps %ymm1, %ymm3, %ymm1
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; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512-NEXT: retq
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%c0 = sitofp <8 x i32> %a0 to <8 x float>
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%c1 = sitofp <8 x i32> %a1 to <8 x float>
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%v0 = fadd <8 x float> %b0, %c0
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%v1 = fadd <8 x float> %b1, %c1
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%res = shufflevector <8 x float> %v0, <8 x float> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x float> %res
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}

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