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petar-avramovicpetar-avramovic
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AMDGPU/GlobalISel: Add regbanklegalize rules for uniform global loads
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‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

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@@ -671,6 +671,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
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.Any({{{UniB256, UniP1}, isAlign4 && isUL}, {{SgprB256}, {SgprP1}}})
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.Any({{{UniB512, UniP1}, isAlign4 && isUL}, {{SgprB512}, {SgprP1}}})
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.Any({{{UniB32, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB32}, {SgprP1}}})
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.Any({{{UniB64, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB64}, {SgprP1}}})
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.Any({{{UniB96, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB96}, {SgprP1}}})
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.Any({{{UniB128, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB128}, {SgprP1}}})
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.Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}})
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.Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}})
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
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define amdgpu_ps void @uniform_load_32(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1, ptr addrspace(1) inreg %ptr2) {
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; CHECK-LABEL: uniform_load_32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: global_load_dword v1, v0, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v1
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; CHECK-NEXT: v_readfirstlane_b32 s1, v2
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; CHECK-NEXT: s_add_i32 s0, s0, s1
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; CHECK-NEXT: v_mov_b32_e32 v1, s0
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; CHECK-NEXT: global_store_dword v0, v1, s[4:5]
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; CHECK-NEXT: s_endpgm
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%load0 = load volatile i32, ptr addrspace(1) %ptr0
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%load1 = load volatile i32, ptr addrspace(1) %ptr1
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%sum = add i32 %load0, %load1
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store i32 %sum, ptr addrspace(1) %ptr2
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ret void
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}
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define amdgpu_ps void @uniform_load_64(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: uniform_load_64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: s_add_i32 s0, s0, s1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: global_store_dword v2, v0, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
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%elt0 = extractelement <2 x i32> %load, i32 0
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%elt1 = extractelement <2 x i32> %load, i32 1
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%sum = add i32 %elt0, %elt1
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store i32 %sum, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps void @uniform_load_96(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: uniform_load_96:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: v_readfirstlane_b32 s4, v2
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; CHECK-NEXT: s_add_i32 s0, s0, s1
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; CHECK-NEXT: s_add_i32 s0, s0, s4
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: global_store_dword v3, v0, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <3 x i32>, ptr addrspace(1) %ptr0
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%elt0 = extractelement <3 x i32> %load, i32 0
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%elt1 = extractelement <3 x i32> %load, i32 1
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%elt2 = extractelement <3 x i32> %load, i32 2
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%sum0 = add i32 %elt0, %elt1
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%sum = add i32 %sum0, %elt2
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store i32 %sum, ptr addrspace(1) %ptr1
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ret void
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}
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define amdgpu_ps void @uniform_load_128(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
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; CHECK-LABEL: uniform_load_128:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: global_load_dwordx4 v[0:3], v4, s[0:1] glc dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: v_readfirstlane_b32 s4, v2
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; CHECK-NEXT: v_readfirstlane_b32 s5, v3
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; CHECK-NEXT: s_add_i32 s0, s0, s1
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; CHECK-NEXT: s_add_i32 s0, s0, s4
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; CHECK-NEXT: s_add_i32 s0, s0, s5
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: global_store_dword v4, v0, s[2:3]
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; CHECK-NEXT: s_endpgm
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%load = load volatile <4 x i32>, ptr addrspace(1) %ptr0
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%elt0 = extractelement <4 x i32> %load, i32 0
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%elt1 = extractelement <4 x i32> %load, i32 1
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%elt2 = extractelement <4 x i32> %load, i32 2
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%elt3 = extractelement <4 x i32> %load, i32 3
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%sum0 = add i32 %elt0, %elt1
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%sum1 = add i32 %sum0, %elt2
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%sum = add i32 %sum1, %elt3
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store i32 %sum, ptr addrspace(1) %ptr1
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ret void
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}

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