Skip to content

Commit 7a0c9f6

Browse files
tonykuttaiTony Varghese
tonykuttai
and
Tony Varghese
authored
[NFC][PowerPC] Pre-commit test case for exploitation of xxeval for the pattern ternary(A,X,or(B,C)) (#143693)
Pre-commit test case for exploitation of `xxeval` for ternary operations of the pattern `ternary(A,X,or(B,C))`. Exploitation of `xxeval` to be added later. Co-authored-by: Tony Varghese <[email protected]>
1 parent 8063330 commit 7a0c9f6

File tree

1 file changed

+268
-0
lines changed

1 file changed

+268
-0
lines changed

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-or.ll

Lines changed: 268 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,268 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
3+
4+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
5+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
6+
7+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
8+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
9+
10+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
11+
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
12+
13+
; Function to test ternary(A, and(B, C), or(B, C)) for <4 x i32>
14+
define <4 x i32> @ternary_A_and_BC_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
15+
; CHECK-LABEL: ternary_A_and_BC_or_BC_4x32:
16+
; CHECK: # %bb.0: # %entry
17+
; CHECK-NEXT: xxleqv v5, v5, v5
18+
; CHECK-NEXT: xxland vs0, v3, v4
19+
; CHECK-NEXT: xxlor vs1, v3, v4
20+
; CHECK-NEXT: vslw v2, v2, v5
21+
; CHECK-NEXT: vsraw v2, v2, v5
22+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
23+
; CHECK-NEXT: blr
24+
entry:
25+
%and = and <4 x i32> %B, %C
26+
%or = or <4 x i32> %B, %C
27+
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %or
28+
ret <4 x i32> %res
29+
}
30+
31+
; Function to test ternary(A, and(B, C), or(B, C)) for <2 x i64>
32+
define <2 x i64> @ternary_A_and_BC_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
33+
; CHECK-LABEL: ternary_A_and_BC_or_BC_2x64:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: xxlxor v5, v5, v5
36+
; CHECK-NEXT: xxland vs0, v3, v4
37+
; CHECK-NEXT: xxlor vs1, v3, v4
38+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
39+
; CHECK-NEXT: vsld v2, v2, v5
40+
; CHECK-NEXT: vsrad v2, v2, v5
41+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
42+
; CHECK-NEXT: blr
43+
entry:
44+
%and = and <2 x i64> %B, %C
45+
%or = or <2 x i64> %B, %C
46+
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %or
47+
ret <2 x i64> %res
48+
}
49+
50+
; Function to test ternary(A, B, or(B, C)) for <4 x i32>
51+
define <4 x i32> @ternary_A_B_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
52+
; CHECK-LABEL: ternary_A_B_or_BC_4x32:
53+
; CHECK: # %bb.0: # %entry
54+
; CHECK-NEXT: xxleqv v5, v5, v5
55+
; CHECK-NEXT: xxlor vs0, v3, v4
56+
; CHECK-NEXT: vslw v2, v2, v5
57+
; CHECK-NEXT: vsraw v2, v2, v5
58+
; CHECK-NEXT: xxsel v2, vs0, v3, v2
59+
; CHECK-NEXT: blr
60+
entry:
61+
%or = or <4 x i32> %B, %C
62+
%res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %or
63+
ret <4 x i32> %res
64+
}
65+
66+
; Function to test ternary(A, B, or(B, C)) for <2 x i64>
67+
define <2 x i64> @ternary_A_B_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
68+
; CHECK-LABEL: ternary_A_B_or_BC_2x64:
69+
; CHECK: # %bb.0: # %entry
70+
; CHECK-NEXT: xxlxor v5, v5, v5
71+
; CHECK-NEXT: xxlor vs0, v3, v4
72+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
73+
; CHECK-NEXT: vsld v2, v2, v5
74+
; CHECK-NEXT: vsrad v2, v2, v5
75+
; CHECK-NEXT: xxsel v2, vs0, v3, v2
76+
; CHECK-NEXT: blr
77+
entry:
78+
%or = or <2 x i64> %B, %C
79+
%res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %or
80+
ret <2 x i64> %res
81+
}
82+
83+
84+
; Function to test ternary(A, C, or(B, C)) for <4 x i32>
85+
define <4 x i32> @ternary_A_C_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
86+
; CHECK-LABEL: ternary_A_C_or_BC_4x32:
87+
; CHECK: # %bb.0: # %entry
88+
; CHECK-NEXT: xxleqv v5, v5, v5
89+
; CHECK-NEXT: xxlor vs0, v3, v4
90+
; CHECK-NEXT: vslw v2, v2, v5
91+
; CHECK-NEXT: vsraw v2, v2, v5
92+
; CHECK-NEXT: xxsel v2, vs0, v4, v2
93+
; CHECK-NEXT: blr
94+
entry:
95+
%or = or <4 x i32> %B, %C
96+
%res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %or
97+
ret <4 x i32> %res
98+
}
99+
100+
; Function to test ternary(A, C, or(B, C)) for <2 x i64>
101+
define <2 x i64> @ternary_A_C_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
102+
; CHECK-LABEL: ternary_A_C_or_BC_2x64:
103+
; CHECK: # %bb.0: # %entry
104+
; CHECK-NEXT: xxlxor v5, v5, v5
105+
; CHECK-NEXT: xxlor vs0, v3, v4
106+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
107+
; CHECK-NEXT: vsld v2, v2, v5
108+
; CHECK-NEXT: vsrad v2, v2, v5
109+
; CHECK-NEXT: xxsel v2, vs0, v4, v2
110+
; CHECK-NEXT: blr
111+
entry:
112+
%or = or <2 x i64> %B, %C
113+
%res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %or
114+
ret <2 x i64> %res
115+
}
116+
117+
118+
; Function to test ternary(A, eqv(B,C), or(B, C)) for <4 x i32>
119+
define <4 x i32> @ternary_A_eqv_BC_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
120+
; CHECK-LABEL: ternary_A_eqv_BC_or_BC_4x32:
121+
; CHECK: # %bb.0: # %entry
122+
; CHECK-NEXT: xxleqv v5, v5, v5
123+
; CHECK-NEXT: xxleqv vs0, v3, v4
124+
; CHECK-NEXT: xxlor vs1, v3, v4
125+
; CHECK-NEXT: vslw v2, v2, v5
126+
; CHECK-NEXT: vsraw v2, v2, v5
127+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
128+
; CHECK-NEXT: blr
129+
entry:
130+
%xor = xor <4 x i32> %B, %C
131+
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
132+
%or = or <4 x i32> %B, %C
133+
%res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %or
134+
ret <4 x i32> %res
135+
}
136+
137+
; Function to test ternary(A, eqv(B,C), or(B, C)) for <2 x i64>
138+
define <2 x i64> @ternary_A_eqv_BC_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
139+
; CHECK-LABEL: ternary_A_eqv_BC_or_BC_2x64:
140+
; CHECK: # %bb.0: # %entry
141+
; CHECK-NEXT: xxlxor v5, v5, v5
142+
; CHECK-NEXT: xxleqv vs0, v3, v4
143+
; CHECK-NEXT: xxlor vs1, v3, v4
144+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
145+
; CHECK-NEXT: vsld v2, v2, v5
146+
; CHECK-NEXT: vsrad v2, v2, v5
147+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
148+
; CHECK-NEXT: blr
149+
entry:
150+
%xor = xor <2 x i64> %B, %C
151+
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
152+
%or = or <2 x i64> %B, %C
153+
%res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %or
154+
ret <2 x i64> %res
155+
}
156+
157+
; Function to test ternary(A, not(C), or(B, C)) for <4 x i32>
158+
define <4 x i32> @ternary_A_not_C_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
159+
; CHECK-LABEL: ternary_A_not_C_or_BC_4x32:
160+
; CHECK: # %bb.0: # %entry
161+
; CHECK-NEXT: xxleqv v5, v5, v5
162+
; CHECK-NEXT: xxlnor vs0, v4, v4
163+
; CHECK-NEXT: xxlor vs1, v3, v4
164+
; CHECK-NEXT: vslw v2, v2, v5
165+
; CHECK-NEXT: vsraw v2, v2, v5
166+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
167+
; CHECK-NEXT: blr
168+
entry:
169+
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
170+
%or = or <4 x i32> %B, %C
171+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %or
172+
ret <4 x i32> %res
173+
}
174+
175+
; Function to test ternary(A, not(C), or(B, C)) for <2 x i64>
176+
define <2 x i64> @ternary_A_not_C_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
177+
; CHECK-LABEL: ternary_A_not_C_or_BC_2x64:
178+
; CHECK: # %bb.0: # %entry
179+
; CHECK-NEXT: xxlxor v5, v5, v5
180+
; CHECK-NEXT: xxlnor vs0, v4, v4
181+
; CHECK-NEXT: xxlor vs1, v3, v4
182+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
183+
; CHECK-NEXT: vsld v2, v2, v5
184+
; CHECK-NEXT: vsrad v2, v2, v5
185+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
186+
; CHECK-NEXT: blr
187+
entry:
188+
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
189+
%or = or <2 x i64> %B, %C
190+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %or
191+
ret <2 x i64> %res
192+
}
193+
194+
; Function to test ternary(A, not(B), or(B, C)) for <4 x i32>
195+
define <4 x i32> @ternary_A_not_B_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
196+
; CHECK-LABEL: ternary_A_not_B_or_BC_4x32:
197+
; CHECK: # %bb.0: # %entry
198+
; CHECK-NEXT: xxleqv v5, v5, v5
199+
; CHECK-NEXT: xxlnor vs0, v3, v3
200+
; CHECK-NEXT: xxlor vs1, v3, v4
201+
; CHECK-NEXT: vslw v2, v2, v5
202+
; CHECK-NEXT: vsraw v2, v2, v5
203+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
204+
; CHECK-NEXT: blr
205+
entry:
206+
%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
207+
%or = or <4 x i32> %B, %C
208+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %or
209+
ret <4 x i32> %res
210+
}
211+
212+
; Function to test ternary(A, not(B), or(B, C)) for <2 x i64>
213+
define <2 x i64> @ternary_A_not_B_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
214+
; CHECK-LABEL: ternary_A_not_B_or_BC_2x64:
215+
; CHECK: # %bb.0: # %entry
216+
; CHECK-NEXT: xxlxor v5, v5, v5
217+
; CHECK-NEXT: xxlnor vs0, v3, v3
218+
; CHECK-NEXT: xxlor vs1, v3, v4
219+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
220+
; CHECK-NEXT: vsld v2, v2, v5
221+
; CHECK-NEXT: vsrad v2, v2, v5
222+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
223+
; CHECK-NEXT: blr
224+
entry:
225+
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
226+
%or = or <2 x i64> %B, %C
227+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %or
228+
ret <2 x i64> %res
229+
}
230+
231+
; Function to test ternary(A, nand(B,C), or(B, C)) for <4 x i32>
232+
define <4 x i32> @ternary_A_nand_BC_or_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) {
233+
; CHECK-LABEL: ternary_A_nand_BC_or_BC_4x32:
234+
; CHECK: # %bb.0: # %entry
235+
; CHECK-NEXT: xxleqv v5, v5, v5
236+
; CHECK-NEXT: xxlnand vs0, v3, v4
237+
; CHECK-NEXT: xxlor vs1, v3, v4
238+
; CHECK-NEXT: vslw v2, v2, v5
239+
; CHECK-NEXT: vsraw v2, v2, v5
240+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
241+
; CHECK-NEXT: blr
242+
entry:
243+
%and = and <4 x i32> %B, %C
244+
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
245+
%or = or <4 x i32> %B, %C
246+
%res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %or
247+
ret <4 x i32> %res
248+
}
249+
250+
; Function to test ternary(A, nand(B,C), or(B, C)) for <2 x i64>
251+
define <2 x i64> @ternary_A_nand_BC_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) {
252+
; CHECK-LABEL: ternary_A_nand_BC_or_BC_2x64:
253+
; CHECK: # %bb.0: # %entry
254+
; CHECK-NEXT: xxlxor v5, v5, v5
255+
; CHECK-NEXT: xxlnand vs0, v3, v4
256+
; CHECK-NEXT: xxlor vs1, v3, v4
257+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
258+
; CHECK-NEXT: vsld v2, v2, v5
259+
; CHECK-NEXT: vsrad v2, v2, v5
260+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
261+
; CHECK-NEXT: blr
262+
entry:
263+
%and = and <2 x i64> %B, %C
264+
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
265+
%or = or <2 x i64> %B, %C
266+
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %or
267+
ret <2 x i64> %res
268+
}

0 commit comments

Comments
 (0)