updated dbg test

Author: Mel-Chen

llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll

@@ -35,14 +35,14 @@ define void @reverse_store(ptr %a, i64 %n) !dbg !4 {
 ; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <vscale x 4 x i64> [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[TMP8]], !dbg [[DBG19:![0-9]+]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = trunc nuw nsw <vscale x 4 x i64> [[TMP7]] to <vscale x 4 x i32>, !dbg [[DBG21:![0-9]+]]
-; CHECK-NEXT:    [[TMP11:%.*]] = zext i32 [[TMP4]] to i64, !dbg [[DBG21]]
-; CHECK-NEXT:    [[TMP12:%.*]] = mul i64 0, [[TMP11]], !dbg [[DBG21]]
-; CHECK-NEXT:    [[TMP13:%.*]] = sub i64 [[TMP11]], 1, !dbg [[DBG21]]
-; CHECK-NEXT:    [[TMP14:%.*]] = mul i64 -1, [[TMP13]], !dbg [[DBG21]]
-; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr i32, ptr [[TMP9]], i64 [[TMP12]], !dbg [[DBG21]]
-; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i32, ptr [[TMP15]], i64 [[TMP14]], !dbg [[DBG21]]
-; CHECK-NEXT:    [[VP_REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP10]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
-; CHECK-NEXT:    call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE]], ptr align 4 [[TMP16]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP11:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[TMP10]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP4]] to i64, !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP13:%.*]] = mul i64 0, [[TMP12]], !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP14:%.*]] = sub i64 [[TMP12]], 1, !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP15:%.*]] = mul i64 -1, [[TMP14]], !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 [[TMP13]], !dbg [[DBG21]]
+; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr i32, ptr [[TMP16]], i64 [[TMP15]], !dbg [[DBG21]]
+; CHECK-NEXT:    call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP11]], ptr align 4 [[TMP18]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG21]]
 ; CHECK-NEXT:    [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
 ; CHECK-NEXT:    [[VEC_IND_NEXT]] = add nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0