Skip to content

Commit f8ab74f

Browse files
RamNalamothuRamNalamothu
authored
[RISC-V] Add schedule information for Qualcomm extensions (#172601)
Add schedule information for the instructions of the following Qualcomm vendor extensions. Xqcia Xqciac Xqcibm Xqcicli Xqcicm Xqcics Xqcili Xqcilia
1 parent 71760f3 commit f8ab74f

File tree

1 file changed

+76
-39
lines changed

1 file changed

+76
-39
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 76 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -468,30 +468,35 @@ class QCIStore_ScaleIdx<bits<4> funct4, string opcodestr>
468468
class QCIRVInstI<bits<4> funct4, string opcodestr>
469469
: RVInstIUnary<{0b000, funct4, 0b00000}, 0b011, OPC_CUSTOM_0,
470470
(outs GPRNoX0:$rd), (ins GPRNoX0:$rs1), opcodestr,
471-
"$rd, $rs1">;
471+
"$rd, $rs1">,
472+
Sched<[WriteIALU, ReadIALU]>;
472473

473474
class QCIRVInstR<bits<4> funct4, string opcodestr>
474475
: RVInstR<{0b000, funct4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
475-
(ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> {
476+
(ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1">,
477+
Sched<[WriteIALU, ReadIALU]> {
476478
let rs2 = 0;
477479
}
478480

479481
class QCIRVInstRR<bits<5> funct5, DAGOperand InTyRs1, string opcodestr>
480482
: RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
481-
(ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">;
483+
(ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">,
484+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
482485

483486
class QCIRVInstRRTied<bits<5> funct5, DAGOperand InTyRs1, string opcodestr>
484487
: RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
485488
(ins GPRNoX0:$rd, InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr,
486-
"$rd, $rs1, $rs2"> {
489+
"$rd, $rs1, $rs2">,
490+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> {
487491
let Constraints = "$rd = $rd_wb";
488492
}
489493

490494
class QCIBitManipRII<bits<3> funct3, bits<2> funct2,
491495
DAGOperand InTyRs1, string opcodestr>
492496
: RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
493497
(ins InTyRs1:$rs1, uimm5_plus1:$width, uimm5:$shamt),
494-
opcodestr, "$rd, $rs1, $width, $shamt"> {
498+
opcodestr, "$rd, $rs1, $width, $shamt">,
499+
Sched<[WriteIALU, ReadIALU]> {
495500
bits<5> shamt;
496501
bits<5> width;
497502

@@ -504,7 +509,8 @@ class QCIBitManipRIITied<bits<3> funct3, bits<2> funct2,
504509
DAGOperand InTyRs1, string opcodestr>
505510
: RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd,
506511
InTyRs1:$rs1, uimm5_plus1:$width, uimm5:$shamt),
507-
opcodestr, "$rd, $rs1, $width, $shamt"> {
512+
opcodestr, "$rd, $rs1, $width, $shamt">,
513+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
508514
let Constraints = "$rd = $rd_wb";
509515
bits<5> shamt;
510516
bits<5> width;
@@ -518,7 +524,8 @@ class QCIRVInstRI<bits<1> funct1, DAGOperand InTyImm11,
518524
string opcodestr>
519525
: RVInstIBase<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
520526
(ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm11:$imm11), opcodestr,
521-
"$rd, $rs1, $imm11"> {
527+
"$rd, $rs1, $imm11">,
528+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
522529
let Constraints = "$rd = $rd_wb";
523530
bits<11> imm11;
524531

@@ -530,7 +537,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
530537
class QCISELECTIICC<bits<3> funct3, string opcodestr>
531538
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
532539
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2),
533-
opcodestr, "$rd, $rs1, $simm1, $simm2"> {
540+
opcodestr, "$rd, $rs1, $simm1, $simm2">,
541+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
534542
let Constraints = "$rd = $rd_wb";
535543
bits<5> simm1;
536544
bits<5> simm2;
@@ -543,7 +551,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
543551
class QCISELECTICC<bits<3> funct3, string opcodestr>
544552
: RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
545553
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2),
546-
opcodestr, "$rd, $rs1, $rs2, $simm2"> {
554+
opcodestr, "$rd, $rs1, $rs2, $simm2">,
555+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> {
547556
let Constraints = "$rd = $rd_wb";
548557
bits<5> simm2;
549558

@@ -554,7 +563,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
554563
class QCISELECTCCI<bits<3> funct3, string opcodestr>
555564
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
556565
(ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3),
557-
opcodestr, "$rd, $imm, $rs2, $rs3"> {
566+
opcodestr, "$rd, $imm, $rs2, $rs3">,
567+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> {
558568
let Constraints = "$rd = $rd_wb";
559569
bits<5> imm;
560570

@@ -565,7 +575,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
565575
class QCISELECTICCI<bits<3> funct3, string opcodestr>
566576
: RVInstR4<0b11, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
567577
(ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2),
568-
opcodestr, "$rd, $imm, $rs2, $simm2"> {
578+
opcodestr, "$rd, $imm, $rs2, $simm2">,
579+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
569580
let Constraints = "$rd = $rd_wb";
570581
bits<5> imm;
571582
bits<5> simm2;
@@ -610,15 +621,17 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
610621
class QCIMVCC<bits<3> funct3, string opcodestr>
611622
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
612623
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
613-
opcodestr, "$rd, $rs1, $rs2, $rs3"> {
624+
opcodestr, "$rd, $rs1, $rs2, $rs3">,
625+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU, ReadIALU]> {
614626
let Constraints = "$rd = $rd_wb";
615627
}
616628

617629
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
618630
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
619631
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
620632
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
621-
opcodestr, "$rd, $rs1, $imm, $rs3"> {
633+
opcodestr, "$rd, $rs1, $imm, $rs3">,
634+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> {
622635
bits<5> imm;
623636

624637
let Constraints = "$rd = $rd_wb";
@@ -782,7 +795,8 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
782795

783796
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
784797
: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, bare_simm32:$imm),
785-
opcodestr, "$rd, $imm", [], InstFormatOther> {
798+
opcodestr, "$rd, $imm", [], InstFormatOther>,
799+
Sched<[WriteIALU, ReadIALU]> {
786800
bits<5> rd;
787801
bits<32> imm;
788802

@@ -797,7 +811,8 @@ class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
797811
class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
798812
: QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
799813
(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
800-
"$rd, $rs1, $imm">;
814+
"$rd, $rs1, $imm">,
815+
Sched<[WriteIALU, ReadIALU]>;
801816

802817
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
803818
class QCIRVInst48EJ<bits<2> func2, string opcodestr>
@@ -892,7 +907,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
892907
def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">;
893908
def QC_WRAPI : RVInstI<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
894909
(ins GPRNoX0:$rs1, uimm11:$imm11), "qc.wrapi",
895-
"$rd, $rs1, $imm11"> {
910+
"$rd, $rs1, $imm11">,
911+
Sched<[WriteIALU, ReadIALU]> {
896912
bits<11> imm11;
897913

898914
let imm12 = {0b0, imm11};
@@ -926,7 +942,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
926942
def QC_INSBI : RVInstIBase<0b001, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
927943
(ins GPRNoX0:$rd, simm5:$imm5, uimm5_plus1:$width,
928944
uimm5:$shamt), "qc.insbi",
929-
"$rd, $imm5, $width, $shamt"> {
945+
"$rd, $imm5, $width, $shamt">,
946+
Sched<[WriteIALU, ReadIALU]> {
930947
let Constraints = "$rd = $rd_wb";
931948
bits<5> imm5;
932949
bits<5> shamt;
@@ -959,11 +976,14 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
959976
def QC_CLO : QCIRVInstI<0b0100, "qc.clo">;
960977
def QC_CTO : QCIRVInstI<0b0101, "qc.cto">;
961978
def QC_BREV32 : QCIRVInstI<0b0110, "qc.brev32">;
962-
def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">;
963-
def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">;
979+
def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">,
980+
Sched<[WriteIALU, ReadIALU]>;
981+
def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">,
982+
Sched<[WriteIALU, ReadIALU]>;
964983
def QC_C_EXTU : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
965984
(ins GPRNoX0:$rd, uimm5ge6_plus1:$width),
966-
"qc.c.extu", "$rd, $width"> {
985+
"qc.c.extu", "$rd, $width">,
986+
Sched<[WriteIALU, ReadIALU]> {
967987
bits<5> rd;
968988
bits<5> width;
969989
let Constraints = "$rd = $rd_wb";
@@ -978,7 +998,8 @@ let Predicates = [HasVendorXqciac, IsRV32] in {
978998
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
979999
def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb),
9801000
(ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm),
981-
"qc.c.muliadd", "$rd, $rs1, $uimm"> {
1001+
"qc.c.muliadd", "$rd, $rs1, $uimm">,
1002+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
9821003
let Constraints = "$rd = $rd_wb";
9831004
bits<5> uimm;
9841005

@@ -989,13 +1010,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
9891010

9901011
def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
9911012
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12),
992-
"qc.muliadd", "$rd, $rs1, $imm12"> {
1013+
"qc.muliadd", "$rd, $rs1, $imm12">,
1014+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
9931015
let Constraints = "$rd = $rd_wb";
9941016
}
9951017

9961018
def QC_SHLADD : RVInstRBase<0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
9971019
(ins GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$shamt),
998-
"qc.shladd", "$rd, $rs1, $rs2, $shamt"> {
1020+
"qc.shladd", "$rd, $rs1, $rs2, $shamt">,
1021+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
9991022
bits<5> shamt;
10001023

10011024
let Inst{31-30} = 0b01;
@@ -1027,26 +1050,39 @@ let Predicates = [HasVendorXqcilsm, IsRV32] in {
10271050
} // Predicates = [HasVendorXqcilsm, IsRV32]
10281051

10291052
let Predicates = [HasVendorXqcicli, IsRV32] in {
1030-
def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">;
1031-
def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">;
1032-
def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">;
1033-
def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">;
1034-
def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">;
1035-
def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">;
1036-
1037-
def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">;
1038-
def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">;
1039-
def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">;
1040-
def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">;
1041-
def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">;
1042-
def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">;
1053+
def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">,
1054+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1055+
def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">,
1056+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1057+
def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">,
1058+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1059+
def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">,
1060+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1061+
def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">,
1062+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1063+
def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">,
1064+
Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>;
1065+
1066+
def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">,
1067+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
1068+
def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">,
1069+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
1070+
def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">,
1071+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
1072+
def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">,
1073+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
1074+
def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">,
1075+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
1076+
def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">,
1077+
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
10431078
} // Predicates = [HasVendorXqcicli, IsRV32]
10441079

10451080
let Predicates = [HasVendorXqcicm, IsRV32] in {
10461081
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
10471082
def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb),
10481083
(ins GPRC:$rd, GPRC:$rs1),
1049-
"qc.c.mveqz", "$rd, $rs1"> {
1084+
"qc.c.mveqz", "$rd, $rs1">,
1085+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
10501086
let Constraints = "$rd = $rd_wb";
10511087

10521088
let Inst{12-10} = 0b011;
@@ -1154,14 +1190,15 @@ let Predicates = [HasVendorXqcilb, IsRV32] in {
11541190
let Predicates = [HasVendorXqcili, IsRV32] in {
11551191
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
11561192
def QC_LI : RVInstU<OPC_OP_IMM_32, (outs GPRNoX0:$rd), (ins simm20_li:$imm20),
1157-
"qc.li", "$rd, $imm20"> {
1193+
"qc.li", "$rd, $imm20">, Sched<[WriteIALU]> {
11581194
let Inst{31} = imm20{19};
11591195
let Inst{30-16} = imm20{14-0};
11601196
let Inst{15-12} = imm20{18-15};
11611197
}
11621198

11631199
def QC_E_LI : RVInst48<(outs GPRNoX0:$rd), (ins bare_simm32:$imm),
1164-
"qc.e.li", "$rd, $imm", [], InstFormatQC_EAI> {
1200+
"qc.e.li", "$rd, $imm", [], InstFormatQC_EAI>,
1201+
Sched<[WriteIALU]> {
11651202
bits<5> rd;
11661203
bits<32> imm;
11671204

0 commit comments

Comments
 (0)