Add FP8×INT4 rowwise GEMM for ROCm (f8i4bf16_rowwise) - #502
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Summary: NOTE: No linked task. Please associate a task with this diff. Adds a ROCm Triton implementation of `mslk::f8i4bf16_rowwise` for FP8 activations and packed INT4 weights while reusing the existing BF16×INT4 kernel. - Defines the operator schema on both CUDA and ROCm so the HIP Python implementation can register reliably. - Specializes the shared kernel with `HAS_X_SCALE`, two BF16 dot operations for FP8-backed inputs, and fused per-row activation scaling. - Adds FP8-specific autotune candidates and pruning while preserving the prior BF16 tuning space. - Validates tensor shapes, dtypes, devices, grouping invariants, and contiguous scale layouts. - Avoids allocating unused split-K workspace for large-M shapes. - Registers the ROCm benchmark implementation and adds a ROCm correctness/dispatch regression test. Upstream PR: meta-pytorch#495 Reviewed By: jwfromm Differential Revision: D116965755
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Summary:
NOTE: No linked task. Please associate a task with this diff.
Adds a ROCm Triton implementation of
mslk::f8i4bf16_rowwisefor FP8 activations and packed INT4 weights while reusing the existing BF16×INT4 kernel.HAS_X_SCALE, two BF16 dot operations for FP8-backed inputs, and fused per-row activation scaling.Upstream PR: #495
Reviewed By: jwfromm
Differential Revision: D116965755