feat: MLX VRAM & performance optimizations for Apple Silicon

[cmoyates]

Summary

• FP16 mixed precision: decoders cast to FP16 (backbone+refiner stay FP32 for accuracy)
• Eliminate CPU-GPU roundtrips: MLX-native preprocessing, slim forward mode (4 outputs vs 9)
• Decoupled backbone resolution: backbone at 1024 while refiner runs at full 2048 — 6.3x faster, 3.4x less peak memory
• Hardened tiled inference: 96px overlap, lazy tile slicing, per-tile cache clearing, bounded memory growth
• Engine API: new params fp16, backbone_size, tile_size, tile_overlap with validation
• Bug fix: mask resize now handles mismatched image/mask dimensions

Benchmark Highlights (M3 Max, 2048x2048)

Config	Median	Peak MB
Baseline (FP32, full backbone)	9,068 ms	27,560
Backbone 1024	1,447 ms	8,044
Tiled 512	3,467 ms	2,626
All optimizations (FP16+bb1024+tiled)	8,450 ms*	2,301

*wall time with real images + resize overhead

Test plan

• 115 tests pass, 0 failures
• Resolution benchmark (256/512/1024)
• Engine config matrix (fp16/fp32 × backbone × tiled at 2048)
• 2048 smoke test with all optimizations — PASSED
• Full results in docs/benchmarks/RESULTS.md

🤖 Generated with Claude Code