This repository contains the hardware design for a 32-bit integer multiplier circuit written in Verilog HDL, using the dadda tree reduction algorithm. This architecture is usually seen in DSP slices, multiplier circuits in general-purpose CPUs and FPGA soft processors. The dadda-tree multiplier is much faster than booth's and shift-add multipliers, while also consuming lesser area and power than wallace-tree and array multipliers, making it a good choice for FPGA soft processors and embedded systems by respecting the constrained available resources while delivering good performance.
The testbench tests the multiplier on various signed/unsigned operands and generates a CSV log file containing columns of operands, expected and obtained results, and error flags. To run the testbench:
iverilog -o mul32_tb.vvp tb/mul32_tb.v src/*.v
vvp mul32_tb.vvpTo visualize the waveforms of various wires, run:
gtkwave mul32_tb.vcd