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mpsl: clock_ctrl: Add MRAM high frequency request to MPSL #20532
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mpsl: clock_ctrl: Add MRAM high frequency request to MPSL #20532
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CI InformationTo view the history of this post, clich the 'edited' button above Inputs:Sources:sdk-nrf: PR head: e2250c7a4bbc8d154f9ff4ee4a0dc1be5f78a643 more detailssdk-nrf:
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Outputs:ToolchainVersion: aedb4c0245 Test Spec & Results: ✅ Success; ❌ Failure; 🟠 Queued; 🟡 Progress; ◻️ Skipped;
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I've added small change to make the frequency more portable/safe. Instead of using a frequency index and |
subsys/mpsl/clock_ctrl/Kconfig
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int "" | ||
default CLOCK_CONTROL_NRF2_NRFS_CLOCK_TIMEOUT_MS if CLOCK_CONTROL_NRF2 | ||
default 1000 |
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there is a prompt but the prompt is empty, this is not right. If this should not be user adjustable, drop the prompt
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In the nRF54h20 SoC the non-volatile memory is located in a global domain which by default configured by nrf2 clock control to run with 64MHz. That makes a code execution time longer so it doesn't fit into radio protocols time requirements. That causes e.g. Bluetooth stack to assert in radio events. To make sure the clock needed for MRAM (non-volatile memory in nRF54h20 SoC) is always setup to highest avaialble frequency MPSL will put a request for the clock to clock control driver. In case there is any other user of the clock that runs from radio core and allows to lower the global domain clock frequency, the clock will still be stay as requested by MPSL. Signed-off-by: Piotr Pryga <[email protected]>
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In the nRF54h20 SoC the non-volatile memory is located in a global domain which by default configured by nrf2 clock control to run with 64MHz. That makes a code execution time longer so it doesn't fit into radio protocols time requirements. That causes e.g. Bluetooth stack to assert in radio events.
To make sure the clock needed for MRAM (non-volatile memory in nRF54h20 SoC) is always setup to highest avaialble frequency MPSL will put a request for the clock to clock control driver. In case there is any other user of the clock that runs from radio core and allows to lower the global domain clock frequency, the clock will still be stay as requested by MPSL.