Added support for Trenz Electronic TE0802

data/te0802.xdc

@@ -0,0 +1,22 @@
+## Clock signal
+set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS18 } [get_ports i_clk];
+create_clock -add -name sys_clk_pin -period 40.00 [get_ports i_clk];
+
+## LED 0
+set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS18 } [get_ports o_led_0];
+
+# PMOD A, Connector J5
+# Connector pin, Package pin, PMOD type 4 UART
+# 1, F8, CTS 
+# 2, F7, TXD
+# 3, E6, RXD
+# 4, E5, RTS
+# 5, GND
+# 6, VCC
+# 7, G6, 
+# 8, G5, 
+# 9, C8, 
+# 10, C7, 
+# 11, GND
+# 12, VCC
+set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 

doc/servant.rst

@@ -248,6 +248,13 @@ FPGA Pin F14 (HSTC GPIO addon connector J2, pin 2) is used for UART output with
 
     fusesoc run --target=sockit servant
 
+Trenz Electronic TE0802
+^^^^^^^^^^^^^^^^^^^^^^^
+
+PMOD A marked J5, pin two, on the board is used for UART output with 115200 baud rate.  
+
+    fusesoc run --target=te0802 servant
+
 TinyFPGA BX
 ^^^^^^^^^^^
 

servant.core

@@ -218,6 +218,12 @@ filesets:
       - servant/servive_clock_gen.v : {file_type : verilogSource}
       - servant/servive.v : {file_type : verilogSource}
 
+  te0802:
+    files:
+      - servant/servant_te0802_clock_gen.v : {file_type : verilogSource}
+      - servant/servant_te0802.v : {file_type : verilogSource}
+      - data/te0802.xdc : {file_type : xdc}
+
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
 
   ulx3s:
@@ -598,6 +604,15 @@ targets:
         device : 5CSXFC6D6F31C6
     toplevel: servive
 
+  te0802:
+    default_tool: vivado
+    description : Trenz Electronic TE0802
+    filesets : [mem_files, soc, te0802]
+    parameters : [memfile, memsize]
+    tools:
+      vivado: {part : xczu2cg-sbva484-1-e}
+    toplevel : servant_te0802
+
   tinyfpga_bx:
     description: TinyFPGA BX
     filesets : [mem_files, soc, service, tinyfpga_bx]

servant/servant_te0802.v

@@ -0,0 +1,33 @@
+`default_nettype none
+module servant_te0802
+  (
+    input wire  i_clk,
+    output wire o_uart_tx,
+    output wire o_led_0
+  );
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      clk;
+   wire      rst;
+   wire      q;
+
+   assign o_uart_tx = q;
+   assign o_led_0 = q;
+
+   servant_te0802_clock_gen
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (clk),
+      .o_rst (rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (clk),
+      .wb_rst (rst),
+      .q      (q));
+
+endmodule

servant/servant_te0802_clock_gen.v

@@ -0,0 +1,45 @@
+`default_nettype none
+module servant_te0802_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   clkfb;
+   wire   locked;
+   reg 	  locked_r;
+
+   // Generate a 32 MHz clock from the 25MHz clock input
+   MMCME4_ADV
+     #(.DIVCLK_DIVIDE    (1),
+       .CLKFBOUT_MULT_F  (48.000),
+       .CLKOUT0_DIVIDE_F (37.5),
+       .CLKIN1_PERIOD    (40.0), //25MHz
+       .STARTUP_WAIT     ("FALSE"))
+   mmcm
+     (.CLKFBOUT    (clkfb),
+      .CLKFBOUTB   (),
+      .CLKOUT0     (o_clk),
+      .CLKOUT0B    (),
+      .CLKOUT1     (),
+      .CLKOUT1B    (),
+      .CLKOUT2     (),
+      .CLKOUT2B    (),
+      .CLKOUT3     (),
+      .CLKOUT3B    (),
+      .CLKOUT4     (),
+      .CLKOUT5     (),
+      .CLKOUT6     (),
+      .CLKIN1      (i_clk),
+      .CLKIN2      (1'b0),
+      .CLKINSEL    (1'b1),
+      .LOCKED      (locked),
+      .PWRDWN      (1'b0),
+      .RST         (1'b0),
+      .CLKFBIN     (clkfb));
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule