Error-[ILWOR] Incorrect Logical Worklib or Reflib

[JackySu]

I followed all the instructions on README and when I reach waveform-generation section, I did

export DV_SIMULATORS=vcs-testharness
export TRACE_FAST=1
bash verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh

I setup vcs/verdi already and intended to run it with vcs, but got the following error when I inspect
$HOME/cva6/verif/sim/out_2025-02-24/vcs-testharness_sim/hello_world.cv64a6_imafdc_sv39.log.iss

make -C /home/ss/cva6/ vcs_build target=cv32a65x gate= top_level=ariane_tb flist=/home/ss/cva6/core/Flist.cva6 defines=
Makefile:153: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
mkdir -p work-dpi
g++ -shared -fPIC -Bsymbolic -I/include -I/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/include -I/home/ss/cva6/tools/verilator/share/verilator/include/vltstd -I/home/ss/riscv-gnu-toolchain/include -I/home/ss/cva6/tools/spike/include -std=c++17 -I/home/ss/cva6/corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/elfloader.cc -o work-dpi/elfloader.o
mkdir -p work-dpi
g++ -shared -fPIC -Bsymbolic -I/include -I/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/include -I/home/ss/cva6/tools/verilator/share/verilator/include/vltstd -I/home/ss/riscv-gnu-toolchain/include -I/home/ss/cva6/tools/spike/include -std=c++17 -I/home/ss/cva6/corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/msim_helper.cc -o work-dpi/msim_helper.o
mkdir -p work-dpi
g++ -shared -fPIC -Bsymbolic -I/include -I/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/include -I/home/ss/cva6/tools/verilator/share/verilator/include/vltstd -I/home/ss/riscv-gnu-toolchain/include -I/home/ss/cva6/tools/spike/include -std=c++17 -I/home/ss/cva6/corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/remote_bitbang.cc -o work-dpi/remote_bitbang.o
mkdir -p work-dpi
g++ -shared -fPIC -Bsymbolic -I/include -I/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/include -I/home/ss/cva6/tools/verilator/share/verilator/include/vltstd -I/home/ss/riscv-gnu-toolchain/include -I/home/ss/cva6/tools/spike/include -std=c++17 -I/home/ss/cva6/corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/SimDTM.cc -o work-dpi/SimDTM.o
mkdir -p work-dpi
g++ -shared -fPIC -Bsymbolic -I/include -I/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/include -I/home/ss/cva6/tools/verilator/share/verilator/include/vltstd -I/home/ss/riscv-gnu-toolchain/include -I/home/ss/cva6/tools/spike/include -std=c++17 -I/home/ss/cva6/corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/SimJTAG.cc -o work-dpi/SimJTAG.o
mkdir -p work-dpi
# Compile C-code and generate .so file
g++ -shared -m64 -o work-dpi/ariane_dpi.so work-dpi/elfloader.o work-dpi/msim_helper.o work-dpi/remote_bitbang.o work-dpi/SimDTM.o work-dpi/SimJTAG.o -L/home/ss/riscv-gnu-toolchain/lib -L/home/ss/cva6/tools/spike/lib -Wl,-rpath,/home/ss/riscv-gnu-toolchain/lib -Wl,-rpath,/home/ss/cva6/tools/spike/lib -lfesvr -lriscv -lyaml-cpp
mkdir -p work-vcs
cd work-vcs &&\
vlogan  -full64 -nc -sverilog +define+ -assert svaext -f /home/ss/cva6/core/Flist.cva6  +incdir+/home/ss/cva6/vendor/pulp-platform/common_cells/include/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/corev_apu/register_interface/include/  +incdir+/home/ss/cva6/corev_apu/tb/common/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/  +incdir+/home/ss/cva6/verif/tb/core/  +incdir+/home/ss/cva6/core/include/  +incdir+/home/ss/cva6/tools/spike/include/disasm/ ../corev_apu/tb/common/mock_uart.sv -timescale=1ns/1ns &&\
vlogan  -full64 -nc -sverilog +define+ /home/ss/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/ss/cva6/corev_apu/tb/axi_intf.sv /home/ss/cva6/corev_apu/register_interface/src/reg_intf.sv /home/ss/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/ss/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv +incdir+core/include/+/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/etc/uvm-1.2/dpi &&\
vlogan  -full64 -nc -sverilog /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.sv /home/ss/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart_wrap.sv &&\
vlogan  -full64 -nc -sverilog -assert svaext +define+ +incdir+/opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/etc/uvm/src /opt/tools/synopsys/vcs/vcs_vO-2018.09-SP2/etc/uvm/src/uvm_pkg.sv  /home/ss/cva6/core/cva6_rvfi.sv /home/ss/cva6/corev_apu/src/ariane.sv /home/ss/cva6/corev_apu/bootrom/bootrom.sv /home/ss/cva6/corev_apu/clint/axi_lite_interface.sv /home/ss/cva6/corev_apu/clint/clint.sv /home/ss/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv /home/ss/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb.sv /home/ss/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv /home/ss/cva6/corev_apu/fpga/src/apb_timer/apb_timer.sv /home/ss/cva6/corev_apu/fpga/src/apb_timer/timer.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv /home/ss/cva6/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/ss/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/ss/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/ss/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/ss/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/ss/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/ss/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/ss/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/ss/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/ss/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_cut.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_join.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_mux.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_demux.sv /home/ss/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv /home/ss/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv /home/ss/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv /home/ss/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv /home/ss/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv /home/ss/cva6/corev_apu/tb/ariane_testharness.sv /home/ss/cva6/corev_apu/tb/ariane_peripherals.sv /home/ss/cva6/corev_apu/tb/rvfi_tracer.sv /home/ss/cva6/corev_apu/tb/common/uart.sv /home/ss/cva6/corev_apu/tb/common/SimDTM.sv /home/ss/cva6/corev_apu/tb/common/SimJTAG.sv  +incdir+/home/ss/cva6/vendor/pulp-platform/common_cells/include/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/corev_apu/register_interface/include/  +incdir+/home/ss/cva6/corev_apu/tb/common/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/  +incdir+/home/ss/cva6/verif/tb/core/  +incdir+/home/ss/cva6/core/include/  +incdir+/home/ss/cva6/tools/spike/include/disasm/ &&\
vlogan  -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
vlogan  -full64 -nc -sverilog -ntb_opts uvm-1.2 /home/ss/cva6/corev_apu/tb/ariane_tb.sv /home/ss/cva6/corev_apu/tb/ariane_testharness.sv /home/ss/cva6/core/cva6_rvfi.sv +define+  +incdir+/home/ss/cva6/vendor/pulp-platform/common_cells/include/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/corev_apu/register_interface/include/  +incdir+/home/ss/cva6/corev_apu/tb/common/  +incdir+/home/ss/cva6/vendor/pulp-platform/axi/include/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/  +incdir+/home/ss/cva6/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/  +incdir+/home/ss/cva6/verif/tb/core/  +incdir+/home/ss/cva6/core/include/  +incdir+/home/ss/cva6/tools/spike/include/disasm/ &&\
vcs -full64  -debug_access+all   -ignore initializer_driver_checks -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb -error="IWNF" \
 +notimingcheck

Warning-[MXIR-W] VCS-MX build is required
  Please make sure that vlogan is from the intended build.


Error-[ILWOR] Incorrect Logical Worklib or Reflib
  The incorrect logical lib is "work".  
  Please check your Synopsys setup file.

I'm a newbie and after some lookup, I was told to put a synopsys_setup.sh in the same folder where vcs was launched, any tip on what I should put into this? Much appreciation!

[github-actions]

👋 Hi there!

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