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8353188: C1: Clean up x86 backend after 32-bit x86 removal #24301

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47f239c
Fix
shipilev Mar 28, 2025
527854e
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shipilev Apr 1, 2025
7726297
Minor whitespace reverts
shipilev Apr 2, 2025
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56 changes: 1 addition & 55 deletions src/hotspot/cpu/x86/c1_CodeStubs_x86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37,66 +37,12 @@

#define __ ce->masm()->

#ifndef _LP64
float ConversionStub::float_zero = 0.0;
double ConversionStub::double_zero = 0.0;

void ConversionStub::emit_code(LIR_Assembler* ce) {
__ bind(_entry);
assert(bytecode() == Bytecodes::_f2i || bytecode() == Bytecodes::_d2i, "other conversions do not require stub");


if (input()->is_single_xmm()) {
__ comiss(input()->as_xmm_float_reg(),
ExternalAddress((address)&float_zero));
} else if (input()->is_double_xmm()) {
__ comisd(input()->as_xmm_double_reg(),
ExternalAddress((address)&double_zero));
} else {
__ push(rax);
__ ftst();
__ fnstsw_ax();
__ sahf();
__ pop(rax);
}

Label NaN, do_return;
__ jccb(Assembler::parity, NaN);
__ jccb(Assembler::below, do_return);

// input is > 0 -> return maxInt
// result register already contains 0x80000000, so subtracting 1 gives 0x7fffffff
__ decrement(result()->as_register());
__ jmpb(do_return);

// input is NaN -> return 0
__ bind(NaN);
__ xorptr(result()->as_register(), result()->as_register());

__ bind(do_return);
__ jmp(_continuation);
}
#endif // !_LP64

void C1SafepointPollStub::emit_code(LIR_Assembler* ce) {
__ bind(_entry);
InternalAddress safepoint_pc(ce->masm()->pc() - ce->masm()->offset() + safepoint_offset());
#ifdef _LP64
__ lea(rscratch1, safepoint_pc);
__ movptr(Address(r15_thread, JavaThread::saved_exception_pc_offset()), rscratch1);
#else
const Register tmp1 = rcx;
const Register tmp2 = rdx;
__ push(tmp1);
__ push(tmp2);

__ lea(tmp1, safepoint_pc);
__ get_thread(tmp2);
__ movptr(Address(tmp2, JavaThread::saved_exception_pc_offset()), tmp1);

__ pop(tmp2);
__ pop(tmp1);
#endif /* _LP64 */

assert(SharedRuntime::polling_page_return_handler_blob() != nullptr,
"polling page return stub not created yet");

Expand Down
12 changes: 4 additions & 8 deletions src/hotspot/cpu/x86/c1_Defs_x86.hpp
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Expand Up @@ -33,15 +33,11 @@ enum {

// registers
enum {
pd_nof_cpu_regs_frame_map = NOT_LP64(8) LP64_ONLY(16), // number of registers used during code emission
pd_nof_cpu_regs_frame_map = 16, // number of registers used during code emission
pd_nof_fpu_regs_frame_map = FloatRegister::number_of_registers, // number of registers used during code emission
pd_nof_xmm_regs_frame_map = XMMRegister::number_of_registers, // number of registers used during code emission

#ifdef _LP64
#define UNALLOCATED 4 // rsp, rbp, r15, r10
#else
#define UNALLOCATED 2 // rsp, rbp
#endif // LP64

pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
Expand All @@ -54,9 +50,9 @@ enum {
pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
pd_first_cpu_reg = 0,
pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0),
pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),
pd_last_cpu_reg = 11,
pd_first_byte_reg = 0,
pd_last_byte_reg = 11,
pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
pd_last_fpu_reg = pd_first_fpu_reg + 7,
pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
Expand Down
38 changes: 5 additions & 33 deletions src/hotspot/cpu/x86/c1_FrameMap_x86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -43,12 +43,8 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
Register reg = r_1->as_Register();
if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
Register reg2 = r_2->as_Register();
#ifdef _LP64
assert(reg2 == reg, "must be same register");
opr = as_long_opr(reg);
#else
opr = as_long_opr(reg2, reg);
#endif // _LP64
} else if (is_reference_type(type)) {
opr = as_oop_opr(reg);
} else if (type == T_METADATA) {
Expand Down Expand Up @@ -111,8 +107,6 @@ LIR_Opr FrameMap::long1_opr;
LIR_Opr FrameMap::xmm0_float_opr;
LIR_Opr FrameMap::xmm0_double_opr;

#ifdef _LP64

LIR_Opr FrameMap::r8_opr;
LIR_Opr FrameMap::r9_opr;
LIR_Opr FrameMap::r10_opr;
Expand All @@ -137,7 +131,6 @@ LIR_Opr FrameMap::r11_metadata_opr;
LIR_Opr FrameMap::r12_metadata_opr;
LIR_Opr FrameMap::r13_metadata_opr;
LIR_Opr FrameMap::r14_metadata_opr;
#endif // _LP64

LIR_Opr FrameMap::_caller_save_cpu_regs[] = {};
LIR_Opr FrameMap::_caller_save_fpu_regs[] = {};
Expand All @@ -157,23 +150,17 @@ XMMRegister FrameMap::nr2xmmreg(int rnr) {
void FrameMap::initialize() {
assert(!_init_done, "once");

assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
assert(nof_cpu_regs == 16, "wrong number of CPU registers");
map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);

#ifndef _LP64
// The unallocatable registers are at the end
map_register(6, rsp);
map_register(7, rbp);
#else
map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9);
map_register(6, r8); r8_opr = LIR_OprFact::single_cpu(6);
map_register(7, r9); r9_opr = LIR_OprFact::single_cpu(7);
map_register(8, r11); r11_opr = LIR_OprFact::single_cpu(8);
map_register(9, r13); r13_opr = LIR_OprFact::single_cpu(9);
map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10);
// r12 is allocated conditionally. With compressed oops it holds
// the heapbase value and is not visible to the allocator.
Expand All @@ -183,15 +170,9 @@ void FrameMap::initialize() {
map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
map_register(14, rsp);
map_register(15, rbp);
#endif // _LP64

#ifdef _LP64
long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
#else
long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
#endif // _LP64
xmm0_float_opr = LIR_OprFact::single_xmm(0);
xmm0_double_opr = LIR_OprFact::double_xmm(0);

Expand All @@ -201,16 +182,12 @@ void FrameMap::initialize() {
_caller_save_cpu_regs[3] = rax_opr;
_caller_save_cpu_regs[4] = rdx_opr;
_caller_save_cpu_regs[5] = rcx_opr;

#ifdef _LP64
_caller_save_cpu_regs[6] = r8_opr;
_caller_save_cpu_regs[7] = r9_opr;
_caller_save_cpu_regs[8] = r11_opr;
_caller_save_cpu_regs[9] = r13_opr;
_caller_save_cpu_regs[10] = r14_opr;
_caller_save_cpu_regs[11] = r12_opr;
#endif // _LP64


_xmm_regs[0] = xmm0;
_xmm_regs[1] = xmm1;
Expand All @@ -220,8 +197,6 @@ void FrameMap::initialize() {
_xmm_regs[5] = xmm5;
_xmm_regs[6] = xmm6;
_xmm_regs[7] = xmm7;

#ifdef _LP64
_xmm_regs[8] = xmm8;
_xmm_regs[9] = xmm9;
_xmm_regs[10] = xmm10;
Expand All @@ -246,7 +221,6 @@ void FrameMap::initialize() {
_xmm_regs[29] = xmm29;
_xmm_regs[30] = xmm30;
_xmm_regs[31] = xmm31;
#endif // _LP64

for (int i = 0; i < 8; i++) {
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
Expand Down Expand Up @@ -276,7 +250,6 @@ void FrameMap::initialize() {
rsp_opr = as_pointer_opr(rsp);
rbp_opr = as_pointer_opr(rbp);

#ifdef _LP64
r8_oop_opr = as_oop_opr(r8);
r9_oop_opr = as_oop_opr(r9);
r11_oop_opr = as_oop_opr(r11);
Expand All @@ -290,7 +263,6 @@ void FrameMap::initialize() {
r12_metadata_opr = as_metadata_opr(r12);
r13_metadata_opr = as_metadata_opr(r13);
r14_metadata_opr = as_metadata_opr(r14);
#endif // _LP64

VMRegPair regs;
BasicType sig_bt = T_OBJECT;
Expand Down
18 changes: 0 additions & 18 deletions src/hotspot/cpu/x86/c1_FrameMap_x86.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -41,13 +41,8 @@
nof_xmm_regs = pd_nof_xmm_regs_frame_map,
nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
first_available_sp_in_frame = 0,
#ifndef _LP64
frame_pad_in_bytes = 8,
nof_reg_args = 2
#else
frame_pad_in_bytes = 16,
nof_reg_args = 6
#endif // _LP64
};

private:
Expand Down Expand Up @@ -81,8 +76,6 @@
static LIR_Opr rdx_metadata_opr;
static LIR_Opr rcx_metadata_opr;

#ifdef _LP64

static LIR_Opr r8_opr;
static LIR_Opr r9_opr;
static LIR_Opr r10_opr;
Expand All @@ -108,28 +101,17 @@
static LIR_Opr r13_metadata_opr;
static LIR_Opr r14_metadata_opr;

#endif // _LP64

static LIR_Opr long0_opr;
static LIR_Opr long1_opr;
static LIR_Opr xmm0_float_opr;
static LIR_Opr xmm0_double_opr;

#ifdef _LP64
static LIR_Opr as_long_opr(Register r) {
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
}
static LIR_Opr as_pointer_opr(Register r) {
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
}
#else
static LIR_Opr as_long_opr(Register r, Register r2) {
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
}
static LIR_Opr as_pointer_opr(Register r) {
return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
}
#endif // _LP64

// VMReg name for spilled physical FPU stack slot n
static VMReg fpu_regname (int n);
Expand Down
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