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    313 repositories

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•48•7•4•Updated Aug 10, 2025Aug 10, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •29•105•5•3•Updated Aug 10, 2025Aug 10, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •24•113•1•1•Updated Aug 10, 2025Aug 10, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •72•275•13•21•Updated Aug 8, 2025Aug 8, 2025

    • chimera

      Public
      Python
      •
      Apache License 2.0
      •4•17•9•3•Updated Aug 8, 2025Aug 8, 2025

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •2•3•2•0•Updated Aug 7, 2025Aug 7, 2025

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •9•14•0•4•Updated Aug 7, 2025Aug 7, 2025

    • fpu_interco

      Public
      SystemVerilog
      •
      Other
      •6•3•0•2•Updated Aug 7, 2025Aug 7, 2025

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •6•9•7•3•Updated Aug 7, 2025Aug 7, 2025

    • magia-sdk

      Public
      C
      •2•3•0•0•Updated Aug 7, 2025Aug 7, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •81•98•21•7•Updated Aug 7, 2025Aug 7, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •820•21•0•7•Updated Aug 7, 2025Aug 7, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •5•17•1•7•Updated Aug 5, 2025Aug 5, 2025

    • transaction-tagger

      Public
      Tag bus transactions by target address
      SystemVerilog
      •
      Other
      •0•1•1•1•Updated Aug 5, 2025Aug 5, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •137•17•0•4•Updated Aug 5, 2025Aug 5, 2025

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •29•125•1•1•Updated Aug 5, 2025Aug 5, 2025

    • fpu_ss

      Public
      CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
      SystemVerilog
      •
      Other
      •8•11•1•1•Updated Aug 5, 2025Aug 5, 2025

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •14•19•2•3•Updated Aug 5, 2025Aug 5, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •304•1.3k•46•17•Updated Aug 5, 2025Aug 5, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •22•10•1•6•Updated Aug 4, 2025Aug 4, 2025

    • pulp-riscv-gnu-toolchain

      Public
      C
      •
      Other
      •52•89•25•0•Updated Aug 4, 2025Aug 4, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •17•73•2•3•Updated Aug 4, 2025Aug 4, 2025

    • pulp-riscv-gcc

      Public
      C
      •
      Other
      •18•7•1•1•Updated Aug 4, 2025Aug 4, 2025

    • dory

      Public
      A tool to deploy Deep Neural Networks on PULP-based SoC's
      Python
      •
      Apache License 2.0
      •22•83•3•4•Updated Aug 4, 2025Aug 4, 2025

    • TeraNoC

      Public
      C
      •
      Apache License 2.0
      •0•2•0•0•Updated Aug 4, 2025Aug 4, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •53•299•3•5•Updated Aug 4, 2025Aug 4, 2025

    • datamover

      Public
      C
      •
      Other
      •0•1•0•2•Updated Aug 2, 2025Aug 2, 2025

    • ace

      Public
      SystemVerilog
      •
      Other
      •5•17•0•1•Updated Aug 1, 2025Aug 1, 2025

    • wakelet

      Public
      Standalone, tiny, and low-power infrastructure to boost the HWPE flexiblity for always-on domains.
      Tcl
      •
      Apache License 2.0
      •0•1•0•0•Updated Jul 31, 2025Jul 31, 2025

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •20•20•3•4•Updated Jul 31, 2025Jul 31, 2025