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Output Directory Changes #5

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@DaleDantis DaleDantis commented Oct 29, 2021 •
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The new Output File Structure is:-

Virtual-FPGA-Lab
   -> out
        -> "Board"
              -> "Design File"
                    -> Dependencies
                    -> Output

Board:- Any of the current implemented Boards
Design File:- Any example file

Also added support for the Nexys-A7 100T

Parameterized the directories of the run.tcl script

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