Forbid inference for input ports that have an output dependency

[VonTum]

module infer_me #(int V) : int a'0 -> int b'V {
  
}
module m : int a'0 -> int b'2 {
  infer_me im

  im.a = a
  reg reg reg reg int a_d = im.a
  b = im.b + a_d
}

This would infer im to be infer_me #(V: 2), yet it would lead to a failure. In this example it may be simple to spot, and errors anyway, but allowing this may have other weird consequences.