Add SPI v1 & v2 (f030 f072)

data/peripherals/F030.yaml

@@ -484,7 +484,7 @@
   address: 0x40013000
   registers:
     kind: spi
-    version: common
+    version: v1
     block: SPI
   rcc:
     bus_clock: PCLK1
@@ -503,7 +503,7 @@
   address: 0x40003800
   registers:
     kind: spi
-    version: common
+    version: v1
     block: SPI
   rcc:
     bus_clock: PCLK1

data/peripherals/F072.yaml

@@ -336,7 +336,7 @@
   address: 0x40013000
   registers:
     kind: spi
-    version: common
+    version: v2
     block: SPI
   rcc:
     bus_clock: PCLK1
@@ -355,7 +355,7 @@
   address: 0x40003800
   registers:
     kind: spi
-    version: common
+    version: v2
     block: SPI
   rcc:
     bus_clock: PCLK1

data/registers/spi_v1.yaml

@@ -0,0 +1,311 @@
+block/SPI:
+  description: Serial peripheral interface.
+  items:
+  - name: CR1
+    description: control register 1.
+    byte_offset: 0
+    fieldset: CR1
+  - name: CR2
+    description: control register 2.
+    byte_offset: 4
+    fieldset: CR2
+  - name: SR
+    description: status register.
+    byte_offset: 8
+    fieldset: SR
+  - name: DR
+    description: data register.
+    byte_offset: 12
+    fieldset: DR
+fieldset/CR1:
+  description: control register 1.
+  fields:
+  - name: CPHA
+    description: Clock phase.
+    bit_offset: 0
+    bit_size: 1
+    enum: CPHA
+  - name: CPOL
+    description: Clock polarity.
+    bit_offset: 1
+    bit_size: 1
+    enum: CPOL
+  - name: MSTR
+    description: Master selection.
+    bit_offset: 2
+    bit_size: 1
+    enum: MSTR
+  - name: BR
+    description: Baud rate control.
+    bit_offset: 3
+    bit_size: 3
+    enum: BR
+  - name: SPE
+    description: SPI enable.
+    bit_offset: 6
+    bit_size: 1
+  - name: LSBFIRST
+    description: Frame format.
+    bit_offset: 7
+    bit_size: 1
+    enum: LSBFIRST
+  - name: SSI
+    description: Internal slave select.
+    bit_offset: 8
+    bit_size: 1
+  - name: SSM
+    description: Software slave management.
+    bit_offset: 9
+    bit_size: 1
+  - name: RXONLY
+    description: Receive only.
+    bit_offset: 10
+    bit_size: 1
+    enum: RXONLY
+  - name: BIDIOE
+    description: Select the direction of transfer in bidirectional mode.
+    bit_offset: 14
+    bit_size: 1
+    enum: BIDIOE
+  - name: BIDIMODE
+    description: Bidirectional data mode enable.
+    bit_offset: 15
+    bit_size: 1
+    enum: BIDIMODE
+fieldset/CR2:
+  description: control register 2.
+  fields:
+  - name: RXDMAEN
+    description: Rx buffer DMA enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: TXDMAEN
+    description: Tx buffer DMA enable.
+    bit_offset: 1
+    bit_size: 1
+  - name: SSOE
+    description: SS output enable.
+    bit_offset: 2
+    bit_size: 1
+  - name: ERRIE
+    description: Error interrupt enable.
+    bit_offset: 5
+    bit_size: 1
+  - name: RXNEIE
+    description: RX buffer not empty interrupt enable.
+    bit_offset: 6
+    bit_size: 1
+  - name: TXEIE
+    description: Tx buffer empty interrupt enable.
+    bit_offset: 7
+    bit_size: 1
+  - name: DS
+    description: Data length.
+    bit_offset: 11
+    bit_size: 1
+  - name: FRXTH
+    description: FIFO reception threshold.
+    bit_offset: 12
+    bit_size: 1
+    enum: FRXTH
+  - name: LDMA_RX
+    description: Last DMA transfer for reception.
+    bit_offset: 13
+    bit_size: 1
+    enum: LDMA_RX
+  - name: LDMA_TX
+    description: Last DMA transfer for transmission.
+    bit_offset: 14
+    bit_size: 1
+    enum: LDMA_TX
+  - name: SLVFM
+    description: Slave fast mode enable.
+    bit_offset: 15
+    bit_size: 1
+fieldset/DR:
+  description: data register.
+  fields:
+  - name: DR
+    description: Data register.
+    bit_offset: 0
+    bit_size: 16
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: RXNE
+    description: Receive buffer not empty.
+    bit_offset: 0
+    bit_size: 1
+  - name: TXE
+    description: Transmit buffer empty.
+    bit_offset: 1
+    bit_size: 1
+  - name: MODF
+    description: Mode fault.
+    bit_offset: 5
+    bit_size: 1
+  - name: OVR
+    description: Overrun flag.
+    bit_offset: 6
+    bit_size: 1
+  - name: BSY
+    description: Busy flag.
+    bit_offset: 7
+    bit_size: 1
+  - name: FRLVL
+    description: FIFO reception level.
+    bit_offset: 9
+    bit_size: 2
+    enum: FRLVL
+  - name: FTLVL
+    description: FIFO Transmission Level.
+    bit_offset: 11
+    bit_size: 2
+    enum: FTLVL
+enum/BIDIMODE:
+  bit_size: 1
+  variants:
+  - name: Unidirectional
+    description: 2-line unidirectional data mode selected
+    value: 0
+  - name: Bidirectional
+    description: 1-line bidirectional data mode selected
+    value: 1
+enum/BIDIOE:
+  bit_size: 1
+  variants:
+  - name: Receive
+    description: Output disabled (receive-only mode)
+    value: 0
+  - name: Transmit
+    description: Output enabled (transmit-only mode)
+    value: 1
+enum/BR:
+  bit_size: 3
+  variants:
+  - name: Div2
+    description: f_PCLK / 2
+    value: 0
+  - name: Div4
+    description: f_PCLK / 4
+    value: 1
+  - name: Div8
+    description: f_PCLK / 8
+    value: 2
+  - name: Div16
+    description: f_PCLK / 16
+    value: 3
+  - name: Div32
+    description: f_PCLK / 32
+    value: 4
+  - name: Div64
+    description: f_PCLK / 64
+    value: 5
+  - name: Div128
+    description: f_PCLK / 128
+    value: 6
+  - name: Div256
+    description: f_PCLK / 256
+    value: 7
+enum/CPHA:
+  bit_size: 1
+  variants:
+  - name: FirstEdge
+    description: The first clock transition is the first data capture edge
+    value: 0
+  - name: SecondEdge
+    description: The second clock transition is the first data capture edge
+    value: 1
+enum/CPOL:
+  bit_size: 1
+  variants:
+  - name: IdleLow
+    description: CK to 0 when idle
+    value: 0
+  - name: IdleHigh
+    description: CK to 1 when idle
+    value: 1
+enum/FRLVL:
+  bit_size: 2
+  variants:
+  - name: Empty
+    description: Rx FIFO Empty
+    value: 0
+  - name: Quarter
+    description: Rx 1/4 FIFO
+    value: 1
+  - name: Half
+    description: Rx 1/2 FIFO
+    value: 2
+  - name: Full
+    description: Rx FIFO full
+    value: 3
+enum/FRXTH:
+  bit_size: 1
+  variants:
+  - name: Half
+    description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
+    value: 0
+  - name: Quarter
+    description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
+    value: 1
+enum/FTLVL:
+  bit_size: 2
+  variants:
+  - name: Empty
+    description: Tx FIFO Empty
+    value: 0
+  - name: Quarter
+    description: Tx 1/4 FIFO
+    value: 1
+  - name: Half
+    description: Tx 1/2 FIFO
+    value: 2
+  - name: Full
+    description: Tx FIFO full
+    value: 3
+enum/LDMA_RX:
+  bit_size: 1
+  variants:
+  - name: Even
+    description: Number of data to transfer for receive is even
+    value: 0
+  - name: Odd
+    description: Number of data to transfer for receive is odd
+    value: 1
+enum/LDMA_TX:
+  bit_size: 1
+  variants:
+  - name: Even
+    description: Number of data to transfer for transmit is even
+    value: 0
+  - name: Odd
+    description: Number of data to transfer for transmit is odd
+    value: 1
+enum/LSBFIRST:
+  bit_size: 1
+  variants:
+  - name: MSBFirst
+    description: Data is transmitted/received with the MSB first
+    value: 0
+  - name: LSBFirst
+    description: Data is transmitted/received with the LSB first
+    value: 1
+enum/MSTR:
+  bit_size: 1
+  variants:
+  - name: Slave
+    description: Slave configuration
+    value: 0
+  - name: Master
+    description: Master configuration
+    value: 1
+enum/RXONLY:
+  bit_size: 1
+  variants:
+  - name: FullDuplex
+    description: Full duplex (Transmit and receive)
+    value: 0
+  - name: OutputDisabled
+    description: Output disabled (Receive-only mode)
+    value: 1