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Add SWD pins and adc_v1b for py32f002b, fix adc_v1 #27

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Merged
decaday merged 2 commits into from
Aug 15, 2025
Merged

Add SWD pins and adc_v1b for py32f002b, fix adc_v1 #27

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a7c0567
Add SWD pins
decaday Aug 15, 2025
80e297a
Add adc_v1b for py32f002b, fix adc_v1
decaday Aug 15, 2025
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24 changes: 24 additions & 0 deletions data/af/PY32F002B.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -165,3 +165,27 @@ USART1:
- af: 1
pin: PB6
signal: TX
DBGMCU:
- af: 0
pin: PA2
signal: SWCLK
- af: 0
pin: PB6
signal: SWDIO
ADC1:
- pin: PB1
signal: IN0
- pin: PA3
signal: IN1
- pin: PA4
signal: IN2
- pin: PA6
signal: IN3
- pin: PA7
signal: IN4
- pin: PC0
signal: IN5
- pin: PB6
signal: IN6
- pin: PB0
signal: IN7
7 changes: 7 additions & 0 deletions data/af/PY32F030.yaml
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Expand Up @@ -586,3 +586,10 @@ ADC1:
signal: IN8
- pin: PB1
signal: IN9
DBGMCU:
- af: 0
pin: PA13
signal: SWDIO
- af: 0
pin: PA14
signal: SWCLK
7 changes: 7 additions & 0 deletions data/af/PY32F07X.yaml
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Expand Up @@ -826,3 +826,10 @@ USB:
signal: DM
- pin: PA12
signal: DP
DBGMCU:
- af: 0
pin: PA13
signal: SWDIO
- af: 0
pin: PA14
signal: SWCLK
7 changes: 7 additions & 0 deletions data/af/PY32F403.yaml
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Expand Up @@ -455,3 +455,10 @@ USART5:
- af: 1
pin: PD5
signal: RTS
DBGMCU:
- af: 0
pin: PA13
signal: SWDIO
- af: 0
pin: PA14
signal: SWCLK
2 changes: 1 addition & 1 deletion data/peripherals/F002B.yaml
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Expand Up @@ -2,7 +2,7 @@
address: 0x40012400
registers:
kind: adc
version: v1
version: v1b
block: ADC
rcc:
bus_clock: PCLK1
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2 changes: 1 addition & 1 deletion data/registers/adc_v1.yaml
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Expand Up @@ -237,7 +237,7 @@ fieldset/CFGR2:
fields:
- name: CKMODE
description: ADC clock mode
bit_offset: 18
bit_offset: 28
bit_size: 4
enum: CKMODE
fieldset/CHSELR:
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