Introduce dt-bindings and initial device tree support for Glymur #517
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Add base DTS file for PMK8850 including PON, GPIO, RTC and SDAM nodes. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Jishnu Prakash <[email protected]> Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add base DTS file for PMH0101 including temp-alarm, GPIO, PWM and flash nodes. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Jishnu Prakash <[email protected]> Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Jishnu Prakash <[email protected]> Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add base DTS file for PMH0110 including temp-alarm and GPIO nodes. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Jishnu Prakash <[email protected]> Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Document Glymur SoC bindings and Compute Reference Device (CRD) board id Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-1-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Introduce initial device tree support for Glymur - Qualcomm's next-generation compute SoC and it's associated Compute Reference Device (CRD) platform. The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD, SRAM, PSCI and pmu nodes. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
…l engines Add device tree support for QUPv3 serial engine protocols on Glymur. Glymur has 24 QUP serial engines across 3 QUP wrappers, each with support of GPI DMA engines. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-4-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Jyothi Kumar Seerapu <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add CPU power domains Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-5-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Maulik Shah <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Enable pdp0 mailbox node on Glymur SoCs. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-6-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add sram and scmi nodes required to have a functional cpu dvfs on Glymur SoCs. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-7-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Enable ipcc and aoss nodes on Glmyur SoCs. Link: lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-8-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add RPMH regulator rails for Glymur CRD. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-9-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add spmi-pmic-arb device for the SPMI PMIC arbiter found on Glymur. It has three subnodes corresponding to the SPMI0, SPMI1 & SPMI2 bus controllers. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-10-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add base DTS file for PMCX0102 along with temp-alarm and GPIO nodes. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-11-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add base DTS file for SMB2370 along with the eUSB repeater node. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-12-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Update the pmh0104.dtsi to include multiple instances of PMH0104 DT nodes, one for each SID assigned to this PMIC on the spmi_bus0 and spmi_bus1 in Glymur CRD board. Take care to avoid compilation issue with the existing nodes by gaurding each PMH0104 nodes with `#ifdef` for its corresponding SID macro. So that only the nodes which have the their SID macro defined are the only ones picked for compilation. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-13-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add multiple instance of PMH0110 DT node, one for each assigned SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur CRD. Take care to avoid compilation issue with the existing nodes by gaurding each PMH0110 nodes with `#ifdef` for its corresponding SID macro. So that only the nodes which have the their SID macro defined are the only ones picked for compilation. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-14-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Include all the PMICs present on the Glymur board into the glymur CRD DTS file. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-15-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add Volume Down/Up keys for Glymur CRD. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-16-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
On Glymur boards, the RTC alarm interrupts are routed to SOCCP subsystems and are not available to APPS. This can cause the RTC probe failure as the RTC IRQ registration will fail in probe. Fix this issue by adding `no-alarm` property in the RTC DT node. This will skip the RTC alarm irq registration and the RTC probe will return success. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-17-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add the pmic glink node with connectors. Link: https://lore.kernel.org/lkml/CAJKOXPd_TgLBy50evLVO2LXS7N2S=yHKO+=AwpQv1On==nDWTQ@mail.gmail.com/ Signed-off-by: Kamal Wadhwa <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Describe PCIe5 controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe5. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-19-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Prudhvi Yarlagadda <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
… signal for pcie5 Add perst, wake and clkreq sideband signals and required regulators in PCIe5 controller and PHY device tree node. Link: https://lore.kernel.org/lkml/20250925-v3_glymur_introduction-v1-20-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Qiang Yu <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add tsens and thermal zones nodes for Glymur SoC. Link: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-21-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Manaf Meethalavalappu Pallikunhi <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Support the display clock controller for GLYMUR SoC. Link: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-22-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
The Glymur USB system contains 3 USB type C ports, and 1 USB multiport controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5 M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the flattened DWC3 QCOM design. Link: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-23-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Wesley Cheng <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Add remoteproc PAS loader for ADSP, CDSP and SoCCP with its SMP2P nodes. Link: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-24-24b601bbecc0@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Pankaj Patil <[email protected]> Signed-off-by: Pradyot Kumar Nayak <[email protected]>
Author
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This PR has dependency on DT bindings, listed below PR |
shashim-quic
merged commit b6ddb1f
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qualcomm-linux:tech/all/dt/glymur
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Added support for Base DT along with Tsens, Display, USB and Remoteproc.