Prepare qcom-next based on tag 'Linux 6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #28
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The QCS8300 Camera clock controller is a derivative of SA8775P, but has few additional clocks and offset differences. Hence, add support for QCS8300 Camera clock controller by extending the SA8775P CamCC. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Imran Shaik <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Patch-mainline: linux-clk @ 01/09/25, 14:27 Signed-off-by: Shiraz Hashim <[email protected]>
Add the global clock controller support for QCS615 SoC. Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Imran Shaik <[email protected]>
* FROMLIST: dt-bindings: arm: Add label in the coresight components Current name of coresight component's folder consists of prefix of the device and the id in the device list. When run 'ls' command, we can get the register address of the device. Take CTI for example, if we want to set the config for modem CTI, but we can't know which CTI is modem CTI from all current information. cti_sys0 -> ../../../devices/platform/soc@0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc@0/13900000.cti/cti_sys1 Add label to show hardware context information of each coresight device. There will be a sysfs node label in each device folder. cat /sys/bus/coresight/devices/cti_sys0/label Link: https://lore.kernel.org/all/[email protected]/ Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Mike Leach <[email protected]> Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: coresight: Add label sysfs node support For some coresight components like CTI and TPDM, there could be numerous of them. From the node name, we can only get the type and register address of the component. We can't identify the HW or the system the component belongs to. Add label sysfs node support for showing the intuitive name of the device. Link: https://lore.kernel.org/all/[email protected]/ Reviewed-by: Mike Leach <[email protected]> Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: dt-bindings: arm: Add CoreSight QMI component description Add new coresight-qmi.yaml file describing the bindings required to define qmi node in the device trees. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: coresight: Add coresight QMI driver Coresight QMI driver uses QMI(Qualcomm Messaging Interface) interfaces to communicate with remote subsystems. Driver gets the instance id and service id from device tree node and init the QMI connections to remote subsystems. Send request function is for other coresight drivers to communicate with remote subsystems. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: dt-bindings: arm: Add qcom,qmi-id for remote etm qcom,qmi-id is required for remote etm driver to find the remote subsystem connection. It is the instance id used by qmi API to communicate with remote processor. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: coresight: Add remote etm support The system on chip (SoC) consists of main APSS(Applications processor subsytem) and additional processors like modem, lpass. Coresight remote etm(Embedded Trace Macrocell) driver is for enabling and disabling the etm trace of remote processors. It uses QMI interface to communicate with remote processors' software and uses coresight framework to configure the connection from remote etm source to TMC sinks. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: arm64: dts: qcom: msm8996: Add coresight qmi node coresight qmi nodes is to init the qmi connection to remote subsystem. qcom,qmi-id is used by remote etm driver to get the remote subsystem connection and send the request. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Mao Jinlong <[email protected]> * FROMLIST: dt-bindings: arm: Add support for Coresight TGU trace The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new coresight-tgu.yaml file to describe the bindings required to define the TGU in the device trees. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight: Add coresight TGU driver Add driver to support Coresight device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight-tgu: Add signal priority support Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight-tgu: Add TGU decode support Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight-tgu: add support to configure next action Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight-tgu: add timer/counter functionality for TGU Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> * FROMLIST: coresight-tgu: add reset node to initialize Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Songwei Chai <[email protected]> --------- Signed-off-by: Mao Jinlong <[email protected]> Signed-off-by: Songwei Chai <[email protected]> Co-authored-by: Mao Jinlong <[email protected]> Co-authored-by: Songwei Chai <[email protected]>
Add prune.config fragment to disable support for non-Qualcomm architectures. This helps reduce boot image size and improves kernel build KPIs by trimming unnecessary configuration options. Signed-off-by: Komal Bajaj <[email protected]>
sa8775p-ride firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-5-b2cf4a20feda@oss.qualcomm.com Co-developed-by: Shivendra Pratap <[email protected]> Signed-off-by: Shivendra Pratap <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Elliot Berman <[email protected]>
Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-1-b2cf4a20feda@oss.qualcomm.com Reviewed-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Elliot Berman <[email protected]>
qcm6490-idp firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-3-b2cf4a20feda@oss.qualcomm.com Co-developed-by: Shivendra Pratap <[email protected]> Signed-off-by: Shivendra Pratap <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Elliot Berman <[email protected]>
…ypes qcs6490-rb3gen2 firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-4-b2cf4a20feda@oss.qualcomm.com Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Elliot Berman <[email protected]>
Now some chips which support 'support_dual_stations' will enable DBS, but will disable DFS. Restructure the ath11k_mac_setup_iface_combinations function to support DBS and DFS compatibility. About 'support_dual_station' feature can refer: https://msgid.link/[email protected] Add a ieee80211_iface_combination to support DBS and DFS compatibility, one combination can support DFS(same with non dual sta), another combination can support DBS. When running different scenarios that will use different ieee80211_iface_combination due to mac80211 will go through all of possible interface combinations. In addition, maximum number of interfaces of these types should be total allowed in this group. The chips affected are: QCA6390 hw2.0 WCN6855 hw2.0 WCN6855 hw2.1 Other chips are not affected. Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-00410-QCAHKSWPL_SILICONZ-2 Tested-on: IPQ6018 hw1.0 AHB WLAN.HK.2.1.0.1-01161-QCAHKSWPL_SILICONZ-1 Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04402-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-05266-QCAHSTSWPLZ_V2_TO_X86-1 Reviewed-by: Baochen Qiang <[email protected]> Reviewed-by: Vasanthakumar Thiagarajan <[email protected]> Acked-by: Jeff Johnson <[email protected]> Tested-by: Mihai Moldovan <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Yu Zhang (Yuriy) <[email protected]> Signed-off-by: Jeff Johnson <[email protected]> Signed-off-by: Miaoqing Pan <[email protected]> Co-authored-by: Yu Zhang(Yuriy) <[email protected]>
SoC vendors have different types of resets and are controlled through
various registers. For instance, Qualcomm chipsets can reboot to a
"download mode" that allows a RAM dump to be collected. Another example
is they also support writing a cookie that can be read by bootloader
during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these
vendor reset types to be implemented without requiring drivers for every
register/cookie.
Add support in PSCI to statically map reboot mode commands from
userspace to a vendor reset and cookie value using the device tree.
A separate initcall is needed to parse the devicetree, instead of using
psci_dt_init because mm isn't sufficiently set up to allocate memory.
Reboot mode framework is close but doesn't quite fit with the
design and requirements for PSCI SYSTEM_RESET2. Some of these issues can
be solved but doesn't seem reasonable in sum:
1. reboot mode registers against the reboot_notifier_list, which is too
early to call SYSTEM_RESET2. PSCI would need to remember the reset
type from the reboot-mode framework callback and use it
psci_sys_reset.
2. reboot mode assumes only one cookie/parameter is described in the
device tree. SYSTEM_RESET2 uses 2: one for the type and one for
cookie.
3. psci cpuidle driver already registers a driver against the
arm,psci-1.0 compatible. Refactoring would be needed to have both a
cpuidle and reboot-mode driver.
Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-2-b2cf4a20feda@oss.qualcomm.com
Signed-off-by: Elliot Berman <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Tested-by: Florian Fainelli <[email protected]>
…or QUP SEs Default pinctrl configurations for all QUP (Qualcomm Universal Peripheral) Serial Engines (SEs) are missing in the SoC device tree. These configurations are required by client teams when enabling any SEs as I2C, SPI, or Serial protocols. Add default pin configurations for Serial Engines (SEs) for all supported protocols, including I2C, SPI, and UART, to the sa8775p device tree. This change facilitates slave device driver clients to enable usecase with minimal modifications. Remove duplicate pin configurations from target-specific file as same pin configuration is included in the SoC device tree. Link: https://lore.kernel.org/r/[email protected] Acked-by: Mukesh Kumar Savaliya <[email protected]> Signed-off-by: Viken Dadhaniya <[email protected]>
…board QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC. Unlike QCS9100, it doesn't have safety monitoring feature of Safety-Island(SAIL) subsystem, which affects thermal management. qcs9075-iq-9075-evk board is based on QCS9075 SOC. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Wasim Nazir <[email protected]>
…/qcs9075 SA8775P has a memory map which caters to the auto specific requirements. QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which inherit the memory map of SA8775P require a slightly different memory map as compared to SA8775P auto parts. This new memory map is applicable for all the IoT boards which inherit the initial SA8775P memory map. This is not applicable for non-IoT boards. Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been introduced as part of firmware updates for IoT. The size and base address have been updated for video PIL carveout compared to SA8775P since it is being brought up for the first time on IoT boards. The base addresses of the rest of the PIL carveouts have been updated to accommodate the change in size of video since PIL regions are relocatable and their functionality is not impacted due to this change. The size of camera pil has also been increased without breaking any feature. The size of trusted apps carveout has also been reduced since it is sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem carveout and its corresponding scm reference has been removed as these are not required for IoT parts. Incorporate these changes in the updated memory map. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pratyush Brahma <[email protected]> Signed-off-by: Prakash Gupta <[email protected]> Signed-off-by: Wasim Nazir <[email protected]>
QCS9075 is an IoT variant of SA8775P SOC, most notably without safety monitoring feature of Safety Island(SAIL) subsystem. Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC, PMICs, Memory-map updates. Use this SOM for qcs9075-iq-9075-evk board. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Wasim Nazir <[email protected]>
Add initial device tree support for IQ-9075-EVK board, based on Qualcomm's QCS9075 SOC. Implement basic features like uart/ufs to enable boot to shell. Link: https://lore.kernel.org/r/[email protected] Co-developed-by: Rakesh Kota <[email protected]> Signed-off-by: Rakesh Kota <[email protected]> Co-developed-by: Sayali Lokhande <[email protected]> Signed-off-by: Sayali Lokhande <[email protected]> Signed-off-by: Wasim Nazir <[email protected]>
Return -ENOMEM if memremap() fails. Don't return success. Fixes: d19b163 ("media: iris: implement video firmware load/unload") Cc: [email protected] Link: https://lore.kernel.org/linux-media/[email protected]/ Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Dikshita Agarwal <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Bryan O'Donoghue <[email protected]> Reviewed-by: Dikshita Agarwal <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
…t_tbl Introduce an optional controller_rst_tbl use to store reset lines used to reset part of the controller. This is necessary for the vpu3 support, when the xo reset line must be asserted separately from the other reset line on power off operation. Factor the iris_init_resets() logic to allow requesting multiple reset tables. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Bryan O'Donoghue <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Reviewed-by: Dikshita Agarwal <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Dikshita Agarwal <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
The IRIS acceleration found in the SM8650 platforms uses the vpu33 hardware version, and requires a slighly different reset and power off sequences in order to properly get out of runtime suspend. Link: https://lore.kernel.org/linux-media/[email protected]/ Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
…rm_gen2 In order to prepare for supporting the SM8650 SoC, move the iris_platform_sm8550.c file into iris_platform_gen2.c that will contain all the common HFI GEN2x structures. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Bryan O'Donoghue <[email protected]> Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. Move the Sm8650 reset tables that differs in a per-SoC platform header, that will contain mode SoC specific data when more codecs are introduced. The SM8650/vpu33 requires more reset lines, but the H.264 decoder capabilities are identical. Link: https://lore.kernel.org/linux-media/[email protected]/ Tested-by: Bryan O'Donoghue <[email protected]> # x1e Dell Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Vikash Garodia <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
Fix the order of compatible strings to make it in alpha numeric order. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Vikash Garodia <[email protected]> Reviewed-by: Dikshita Agarwal <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
Add platform data for QCS8300, which has different capabilities compared to SM8550. Introduce a QCS8300 header that defines these capabilities. Link: https://lore.kernel.org/linux-media/[email protected]/ Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Vikash Garodia <[email protected]> Reviewed-by: Dikshita Agarwal <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Hans Verkuil <[email protected]>
Add support for vadc and adc-tm channels which are used for monitoring thermistors present on the platform. - Add the necessary includes for qcom,spmi-adc7-pm7325 and qcom,spmi-adc7-pmk8350. - Add thermal zones for quiet-thermal, sdm-skin-thermal, and xo-thermal, and define their polling delays and thermal sensors. - Configure the pm7325_temp_alarm node to use the pmk8350_vadc channel for thermal monitoring. - Configure the pmk8350_adc_tm node to enable its thermal sensors and define their registers and settings. - Configure the pmk8350_vadc node to define its channels and settings Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rakesh Kota <[email protected]>
Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC which connected with PMICs on QCS8300 boards. Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-1-ee94642279ff@quicinc.com Signed-off-by: Tingguo Cheng <[email protected]>
Enable PMIC and PMIC peripherals for qcs8300-ride board. The qcs8 300-ride uses 2 pmics(pmm8620au:0,pmm8650au:1) on the board, which are variants of pmm8654au used on sa8775p/qcs9100 -ride(4x pmics). Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-2-ee94642279ff@quicinc.com Signed-off-by: Tingguo Cheng <[email protected]>
Add RTC node, the RTC is controlled by PMIC device via spmi bus. Signed-off-by: Tingguo Cheng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Dmitry Baryshkov <[email protected]>
…d card Document the bindings for the Qualcomm QCS9100 and QCS9075 board specific sound card. The bindings are the same as for other newer Qualcomm ADSP sound cards, thus keep them in existing qcom,sm8250.yaml file, even though Linux driver is separate. Signed-off-by: Mohammad Rafi Shaik <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]>
… QCS9075 Add compatibles for sound card on Qualcomm QCS9100 and QCS9075 boards. Signed-off-by: Mohammad Rafi Shaik <[email protected]> Reviewed-by: Srinivas Kandagatla <[email protected]> Link: https://patch.msgid.link/[email protected] Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Mark Brown <[email protected]>
…9370 headset codec Add nodes for WSA8830 speakers and WCD9370 headset codec on qcm6490-idp board. Enable lpass macros along with audio support pin controls. Co-developed-by: Prasad Kumpatla <[email protected]> Signed-off-by: Prasad Kumpatla <[email protected]> Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Mohammad Rafi Shaik <[email protected]>
Add the sound card node with tested playback over WSA8835 speakers, digital on-board mics along with wcd9370 headset playabck and record. Co-developed-by: Prasad Kumpatla <[email protected]> Signed-off-by: Prasad Kumpatla <[email protected]> Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Mohammad Rafi Shaik <[email protected]>
Correct the ngpios entry to account for the UFS_RESET pin being exported as a GPIO in addition to the real GPIOs, allowing the UFS driver to toggle it. Fixes: b698f36 ("pinctrl: qcom: add the tlmm driver for QCS615 platform") Signed-off-by: Lijuan Gao <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yuanjie Yang <[email protected]>
… for qcs615 Correct the gpio-ranges in the QCS615 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Link: https://lore.kernel.org/r/[email protected] Fixes: 55c487e ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer") Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Lijuan Gao <[email protected]>
… for qcs8300 Correct the gpio-ranges in the QCS8300 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Link: https://lore.kernel.org/r/[email protected] Fixes: 5778535 ("dt-bindings: pinctrl: describe qcs8300-tlmm") Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Lijuan Gao <[email protected]>
Correct the ngpios entry to account for the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory and is exported as GPIOs in addition to the real GPIOs, allowing the UFS driver to toggle it. Link: https://lore.kernel.org/r/[email protected] Fixes: 0c4cd2c ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms") Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Lijuan Gao <[email protected]>
Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Salendarsingh Gaud <[email protected]>
…/pub/scm/linux/kernel/git/torvalds/linux.git Merge following topic branches into v6.15 base: tech/bsp/clk 8310781 tech/bsp/pinctrl d7e196c tech/debug/hwtracing 9982cba tech/mm/audio/all a0a1b5c tech/mm/video 2705b45 tech/net/ath 5bc89ad tech/pm/power 1eeed9b tech/all/dt/qcs6490 f08a96d tech/all/dt/qcs9100 de711b0 tech/all/dt/qcs8300 a7787e1 tech/all/dt/qcs615 0209969 tech/all/config a58db88
The files generated by gen_header.py capture the source path to the input files and the date. While that can be informative, it varies based on where and when the kernel was built as the full path is captured. Since all of the files that this tool is run on is under the drivers directory, this modifies the application to strip all of the path before drivers. Additionally it prints <stripped> instead of the date. Signed-off-by: Ryan Eatmon <[email protected]> Signed-off-by: Bruce Ashfield <[email protected]> Link: https://lore.kernel.org/dri-devel/[email protected]/ Signed-off-by: Viswanath Kraleti <[email protected]>
Command DB is a database in the shared memory of QCOM SoCs, that provides a mapping between resource key and the resource address for a system resource managed by a remote processor. The data is stored in a shared memory region and is loaded by the remote processor. Therefore, enabling Command DB ensures that those resources function properly. Signed-off-by: Lijuan Gao <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Upstream-Status: Backport [https://lore.kernel.org/r/[email protected]] Signed-off-by: Yuanjie Yang <[email protected]>
Signed-off-by: Salendarsingh Gaud <[email protected]>
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tech/mm/drm aa742d7
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