Compile to ZZ gate instead of MS for Forte backends when transpiling …

…to native IonQ gates (#6973) * Use ZZ gate instead of MS when commpiling to native IonQ gates for forte backends. * Fixing CI errors. * Move code around. * Add parathesis to exception. * NotImplemented -> NotImplementedError * return -> raise --------- Co-authored-by: Pavol Juhas <[email protected]>
quantumlib · Feb 6, 2025 · 14d61c8 · 14d61c8
1 parent d589bfc
commit 14d61c8
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Showing 2 changed files with 31 additions and 11 deletions.
diff --git a/cirq-ionq/cirq_ionq/ionq_native_target_gateset.py b/cirq-ionq/cirq_ionq/ionq_native_target_gateset.py
@@ -23,7 +23,7 @@
 from cirq import linalg
 from cirq import ops
 
-from cirq_ionq.ionq_native_gates import GPIGate, GPI2Gate, MSGate
+from cirq_ionq.ionq_native_gates import GPIGate, GPI2Gate, MSGate, ZZGate
 
 
 class IonqNativeGatesetBase(cirq.TwoQubitCompilationTargetGateset):
@@ -121,13 +121,7 @@ def _hadamard(self, qubit):
         return [GPI2Gate(phi=0.25).on(qubit), GPIGate(phi=0).on(qubit)]
 
     def _cnot(self, *qubits):
-        return [
-            GPI2Gate(phi=1 / 4).on(qubits[0]),
-            MSGate(phi0=0, phi1=0).on(qubits[0], qubits[1]),
-            GPI2Gate(phi=1 / 2).on(qubits[1]),
-            GPI2Gate(phi=1 / 2).on(qubits[0]),
-            GPI2Gate(phi=-1 / 4).on(qubits[0]),
-        ]
+        raise NotImplementedError()
 
     def decompose_all_to_all_connect_ccz_gate(
         self, ccz_gate: 'cirq.CCZPowGate', qubits: Tuple['cirq.Qid', ...]
@@ -199,13 +193,21 @@ def __init__(self, *, atol: float = 1e-8):
     def __repr__(self) -> str:
         return f'cirq_ionq.AriaNativeGateset(atol={self.atol})'
 
+    def _cnot(self, *qubits):
+        return [
+            GPI2Gate(phi=1 / 4).on(qubits[0]),
+            MSGate(phi0=0, phi1=0).on(qubits[0], qubits[1]),
+            GPI2Gate(phi=1 / 2).on(qubits[1]),
+            GPI2Gate(phi=1 / 2).on(qubits[0]),
+            GPI2Gate(phi=-1 / 4).on(qubits[0]),
+        ]
+
 
 class ForteNativeGateset(IonqNativeGatesetBase):
     """Target IonQ native gateset for compiling circuits.
 
     The gates forming this gateset are:
-    GPIGate, GPI2Gate, MSGate
-    Note: in the future ZZGate might be added here.
+    GPIGate, GPI2Gate, ZZGate
     """
 
     def __init__(self, *, atol: float = 1e-8):
@@ -214,7 +216,21 @@ def __init__(self, *, atol: float = 1e-8):
         Args:
             atol: A limit on the amount of absolute error introduced by the decomposition.
         """
-        super().__init__(GPIGate, GPI2Gate, MSGate, ops.MeasurementGate, atol=atol)
+        super().__init__(GPIGate, GPI2Gate, ZZGate, ops.MeasurementGate, atol=atol)
 
     def __repr__(self) -> str:
         return f'cirq_ionq.ForteNativeGateset(atol={self.atol})'
+
+    def _cnot(self, *qubits):
+        return [
+            GPI2Gate(phi=0).on(qubits[1]),
+            GPIGate(phi=-0.125).on(qubits[1]),
+            GPI2Gate(phi=0.5).on(qubits[1]),
+            ZZGate(theta=0.25).on(qubits[0], qubits[1]),
+            GPI2Gate(phi=0.75).on(qubits[0]),
+            GPIGate(phi=0.125).on(qubits[0]),
+            GPI2Gate(phi=0.5).on(qubits[0]),
+            GPI2Gate(phi=1.25).on(qubits[1]),
+            GPIGate(phi=0.5).on(qubits[1]),
+            GPI2Gate(phi=0.5).on(qubits[1]),
+        ]
diff --git a/cirq-ionq/cirq_ionq/ionq_native_target_gateset_test.py b/cirq-ionq/cirq_ionq/ionq_native_target_gateset_test.py
@@ -49,6 +49,10 @@ def test_equality_aria():
     eq = cirq.testing.EqualsTester()
     eq.add_equality_group(AriaNativeGateset(atol=1e-6))
     eq.add_equality_group(AriaNativeGateset(atol=1e-5))
+
+
+def test_equality_forte():
+    eq = cirq.testing.EqualsTester()
     eq.add_equality_group(ForteNativeGateset(atol=1e-6))
     eq.add_equality_group(ForteNativeGateset(atol=1e-5))