WALKER - FAST ACCURATE MEMORY TEST CODE FOR FPGAs

A implementation on FPGA of an efficient SRAM memory test algorithm for embedded systems.

Overview • Development • Releases • License

Overview

This project implements a memory test in Verilog and VHDL, based on a C-language algorithm available at Barr Group. The original C implementation is an efficient solution for diagnosing failures in embedded systems and ensuring RAM integrity. The VHDL and Verilog adaptation follows the same principles and consists of three main functions, each designed to verify specific aspects of memory operation.

Development

The project repository is structured into t he following directories:

• doc/ - Contains project documentation, including diagrams and flowcharts.
• hdl/ - Contains the HDL source files for implementation.

Releases

The latest releases of this project can be found here.

License

This project is licensed under the GNU General Public License v3.0. For more details, refer to the LICENSE file.