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target/riscv: dont set mcause and mstatus as cachable #1217

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Merged
merged 1 commit into from
Jan 31, 2025
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target/riscv: dont set mcause and mstatus as cachable #1217

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2 changes: 0 additions & 2 deletions src/target/riscv/riscv_reg_impl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -204,9 +204,7 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
case GDB_REGNO_MISA:
case GDB_REGNO_DCSR:
case GDB_REGNO_DSCRATCH0:
case GDB_REGNO_MSTATUS:
case GDB_REGNO_MEPC:
case GDB_REGNO_MCAUSE:
case GDB_REGNO_SATP:
/*
* WARL registers might not contain the value we just wrote, but
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