Add dcsr cetrig control

.github/workflows/linux-build.yml

@@ -5,7 +5,7 @@ name: Linux Build
 jobs:
   # 32-bit, clang
   build32:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     env:
       CFLAGS: -m32
       CC: clang

doc/openocd.texi

@@ -11437,6 +11437,13 @@ action pairs.
 @end itemize
 @end itemize
 
+@itemize
+@item @code{-cetrig} @option{disable}|@option{enable} -- sets the @code{cetrig}
+field for dcsr. Defaults to @option{disable}.
+
+@item @code{cget} return a @code{cetrig} state.
+@end itemize
+
 @subsection RISC-V Debug Configuration Commands
 
 @deffn {Command} {riscv dump_sample_buf} [base64]

src/target/riscv/debug_defines.c

@@ -1,7 +1,5 @@
-/*
- * This file is auto-generated by running 'make debug_defines' in
- * https://github.com/riscv/riscv-debug-spec/ (40b9a05)
- */
+/* SPDX-License-Identifier: BSD-2-Clause OR CC-BY-4.0 */
+/* This file was auto-generated by running 'make debug_defines' in https://github.com/riscv/riscv-debug-spec/ (22a7576) */
 
 #include "debug_defines.h"
 #include <stddef.h>
@@ -222,6 +220,17 @@ static const char *csr_dcsr_debugver_values[16] = {
 	[4] = "1_0",
 	[15] = "custom"
 };
+static const char *csr_dcsr_extcause_values[8] = {
+	[0] = "critical_error"
+};
+static const char *csr_dcsr_cetrig_values[2] = {
+	[0] = "disabled",
+	[1] = "enabled"
+};
+static const char *csr_dcsr_pelp_values[2] = {
+	[0] = "NO_LP_EXPECTED",
+	[1] = "LP_EXPECTED"
+};
 static const char *csr_dcsr_ebreakvs_values[2] = {
 	[0] = "exception",
 	[1] = "debug_mode"
@@ -260,7 +269,8 @@ static const char *csr_dcsr_cause_values[8] = {
 	[3] = "haltreq",
 	[4] = "step",
 	[5] = "resethaltreq",
-	[6] = "group"
+	[6] = "group",
+	[7] = "other"
 };
 static const char *csr_dcsr_mprven_values[2] = {
 	[0] = "disabled",
@@ -350,6 +360,20 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_debugver(riscv_debug_reg_ctx_t
 	return result;
 }
 
+static riscv_debug_reg_field_list_t csr_dcsr_get_extcause(riscv_debug_reg_ctx_t context)
+{
+	riscv_debug_reg_field_list_t result = {
+		.field = {
+			.name = "extcause",
+			.lsb = 0x18,
+			.msb = 0x1a,
+			.values = csr_dcsr_extcause_values
+		},
+		.get_next = csr_dcsr_get_debugver
+	};
+	return result;
+}
+
 static riscv_debug_reg_field_list_t csr_dcsr_get_step(riscv_debug_reg_ctx_t context)
 {
 	riscv_debug_reg_field_list_t result = {
@@ -359,7 +383,35 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_step(riscv_debug_reg_ctx_t cont
 			.msb = 2,
 			.values = NULL
 		},
-		.get_next = csr_dcsr_get_debugver
+		.get_next = csr_dcsr_get_extcause
+	};
+	return result;
+}
+
+static riscv_debug_reg_field_list_t csr_dcsr_get_cetrig(riscv_debug_reg_ctx_t context)
+{
+	riscv_debug_reg_field_list_t result = {
+		.field = {
+			.name = "cetrig",
+			.lsb = 0x13,
+			.msb = 0x13,
+			.values = csr_dcsr_cetrig_values
+		},
+		.get_next = csr_dcsr_get_step
+	};
+	return result;
+}
+
+static riscv_debug_reg_field_list_t csr_dcsr_get_pelp(riscv_debug_reg_ctx_t context)
+{
+	riscv_debug_reg_field_list_t result = {
+		.field = {
+			.name = "pelp",
+			.lsb = 0x12,
+			.msb = 0x12,
+			.values = csr_dcsr_pelp_values
+		},
+		.get_next = csr_dcsr_get_cetrig
 	};
 	return result;
 }
@@ -373,7 +425,7 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakvs(riscv_debug_reg_ctx_t
 			.msb = 0x11,
 			.values = csr_dcsr_ebreakvs_values
 		},
-		.get_next = csr_dcsr_get_step
+		.get_next = csr_dcsr_get_pelp
 	};
 	return result;
 }
@@ -692,12 +744,11 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t c
 
 static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context)
 {
-	assert(context.XLEN.is_set);
 	riscv_debug_reg_field_list_t result = {
 		.field = {
 			.name = "data",
 			.lsb = 0,
-			.msb = (context.XLEN.value + -1),
+			.msb = 0x1f,
 			.values = NULL
 		},
 		.get_next = NULL
@@ -707,12 +758,11 @@ static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t
 
 static riscv_debug_reg_field_list_t csr_mcontext_get_hcontext(riscv_debug_reg_ctx_t context)
 {
-	assert(context.XLEN.is_set);
 	riscv_debug_reg_field_list_t result = {
 		.field = {
 			.name = "hcontext",
 			.lsb = 0,
-			.msb = (context.XLEN.value + -1),
+			.msb = 0xd,
 			.values = NULL
 		},
 		.get_next = NULL
@@ -1974,7 +2024,7 @@ static riscv_debug_reg_field_list_t csr_textra64_get_sbytemask(riscv_debug_reg_c
 		.field = {
 			.name = "sbytemask",
 			.lsb = 0x24,
-			.msb = 0x28,
+			.msb = 0x27,
 			.values = NULL
 		},
 		.get_next = csr_textra64_get_mhselect
@@ -1988,7 +2038,7 @@ static riscv_debug_reg_field_list_t csr_textra64_get_svalue(riscv_debug_reg_ctx_
 		.field = {
 			.name = "svalue",
 			.lsb = 2,
-			.msb = 0x23,
+			.msb = 0x21,
 			.values = NULL
 		},
 		.get_next = csr_textra64_get_sbytemask