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Trap handler relies on reset mtvec.MODE; cores that reset to vectored (cv32e40p) get mismatched trap-vector signatures in InterruptsSm

bug

Test FrameworkIssue or pull request related to the test selection/runtime frameworkIssue or pull request related to the test selection/runtime framework

Status: Open.

#1590 In riscv/riscv-arch-test;

· karabambus opened on May 27, 2026

Ssstrict tests should have more complete coverage of OP-VE encoding space

enhancementNew feature or requestNew feature or request

Status: Open.

#1588 In riscv/riscv-arch-test;

· davidharrishmc opened on May 27, 2026

Has GCC stabilized enough to be installed without building from source?

enhancementNew feature or requestNew feature or request

Status: Open.

#1587 In riscv/riscv-arch-test;

· davidharrishmc opened on May 27, 2026

Trap handler default setup assumes direct mtvec mode, vectored-only cores get mismatched trap-vector signatures

bug

Test FrameworkIssue or pull request related to the test selection/runtime frameworkIssue or pull request related to the test selection/runtime framework

Status: Open.

#1574 In riscv/riscv-arch-test;

· karabambus opened on May 25, 2026

Zicsr tests fail to compile for U-mode cores without F, V, or Zicntr

bug

Status: Open.

#1572 In riscv/riscv-arch-test;

· karabambus opened on May 25, 2026

MTIME #ifdef guards in InterruptsSm testgen are incomplete - testcase execute even when MTIME is absent

bug

Test FrameworkIssue or pull request related to the test selection/runtime frameworkIssue or pull request related to the test selection/runtime framework

Status: Open.

#1543 In riscv/riscv-arch-test;

· karabambus opened on May 20, 2026

PMP grain used as immediate when it can be more than 12 bits

bug

Test FrameworkIssue or pull request related to the test selection/runtime frameworkIssue or pull request related to the test selection/runtime framework

Status: Open.

#1539 In riscv/riscv-arch-test;

· henrikg-qc opened on May 19, 2026

Sm-00 fails: no configuration for mcounteren read-only zero while U-mode is present

Needs SAIL SupportFeature not yet supported in sail-riscvFeature not yet supported in sail-riscv

Status: Open.

#1502 In riscv/riscv-arch-test;

· karabambus opened on May 14, 2026

[PROPOSAL] M-Mode ACT4 Firmware Runner & Hardware Validation - VisionFive 2 + Milk-V Jupiter

Status: Open.

#1482 In riscv/riscv-arch-test;

· Jjateen opened on May 11, 2026

Add vector illegal instruction tests for reserved vtype settings (vsetvli/vsetvl/vsetivli)

Status: Open.

#1452 In riscv/riscv-arch-test;

· UmerShahidengr opened on May 7, 2026

vstart tests currently disabled

Status: Open.

#1445 In riscv/riscv-arch-test;

· georgiatai opened on May 6, 2026

Reduce size of compiled tests

enhancementNew feature or requestNew feature or request

Status: Open.

#1442 In riscv/riscv-arch-test;

· ZiaCheemaGit opened on May 6, 2026