v0.34.0

• Revert #711
• Add defmt impls for TryFromInterruptError, riscv interrupt enums
• Fix calculating modifiedWriteValues bitmasks with field arrays
• Fix building without yaml feature
• Compatibility with riscv 0.12 and riscv-rt 0.13
• Add riscv_config section in settings.yaml
  It uses riscv-pac traits and standard riscv-peripheral peripherals.
• Add settings.yaml file for target-specific settings.
• Add warning about indexing register arrays
• Skip generating .add(0) and 1 * in accessors
• Bump MSRV of generated code to 1.76
• move must_use from methods to generic type
• breaking change Return raw writtened value
• Add from_write, from_write_with_zero, and from_modify register modifiers
  with generic return value
• InterruptNumber is no longer implemented for Xtensa peripheral interrupts

v0.33.5

• Fix STM32-patched CI
• Fix enumeratedValues with isDefault only
• Fix invalid Punct error from proc_macro2
• Run espressif tests on nightly-2024-09-25 to workaround CI failures

v0.33.4

• Add html-url option to access svdtools html files from docs
• Move Reg in separate file
• Use warning class in docs
• Refactor Accessor

v0.33.3

• Yet more clean field & register Debug

v0.33.2

• Remove unneeded format_args in register Debug impl

v0.33.1

• Add checked set for not full safe fields

v0.33.0

• Add IsEnum constraint for FieldWriters (fix variant safety)
• Make field writer bits always unsafe, add set for safe writing
• Fix bit writer type for ModifiedWriteValues::ZeroToSet

v0.32.0

• Bump MSRV to 1.74
• generic unsafe W::bits + safe W::set
• Add base-address-shift config flag
• Use PascalCase for type idents, fix case changing bugs, add --ident-format (-f) option flag
• Add enum_read_name for read-only enums, RWEnum helper
• Reexport enums inside register again
• Add DimSuffix helper trait

v0.31.5

• move in RegisterBlock::reg_iter implementation (iterator of register/cluster array)
• Fix cargo doc constants generation

v0.31.4

• Custom prefix/case/suffix for identifiers (by svd2rust.toml config file)