sinara-hw · pathfinder49 · Mar 2, 2020 · Mar 2, 2020 · Mar 2, 2020 · Mar 2, 2020
diff --git a/PCB/Fastino.PCBDOC b/PCB/Fastino.PCBDOC
diff --git a/PCB/Fastino.PrjPCB b/PCB/Fastino.PrjPCB
diff --git a/PCB/Fastino.PrjPCBVariants b/PCB/Fastino.PrjPCBVariants
diff --git a/PCB/Fastino.schdoc b/PCB/Fastino.schdoc
diff --git a/PCB/Fastino_DAC_Series_Termination.SchDoc b/PCB/Fastino_DAC_Series_Termination.SchDoc
diff --git a/PCB/Fastino_DAC_channel.SchDoc b/PCB/Fastino_DAC_channel.SchDoc
diff --git a/PCB/Fastino_FPGA.SchDoc b/PCB/Fastino_FPGA.SchDoc
diff --git a/PCB/Fastino_FPGA_Config.Harness b/PCB/Fastino_FPGA_Config.Harness
@@ -1,2 +1 @@
 FPGA_CFG=FPGA_CSBSEL0,FPGA_CSBSEL1,FPGA_SDO,FPGA_SDI,FPGA_SCK,FPGA_SS,FPGA_CDONE,FPGA_CRESET
-I2C=SCL,SDA
diff --git a/PCB/Fastino_FPGA_Config.SchDoc b/PCB/Fastino_FPGA_Config.SchDoc
diff --git a/PCB/Fastino_FPGA_LVDS.SchDoc b/PCB/Fastino_FPGA_LVDS.SchDoc
diff --git a/PCB/Fastino_Supply.SchDoc b/PCB/Fastino_Supply.SchDoc
diff --git a/SIM_CALC/Fastino_Power_Budget.xlsx b/SIM_CALC/Fastino_Power_Budget.xlsx
Original file line number	Diff line number	Diff line change
		@@ -1,2 +1 @@
		FPGA_CFG=FPGA_CSBSEL0,FPGA_CSBSEL1,FPGA_SDO,FPGA_SDI,FPGA_SCK,FPGA_SS,FPGA_CDONE,FPGA_CRESET
		I2C=SCL,SDA