- Create an SVG file where each circuit node is in an SVG group, and give the group a unique (hopefully meaningful) name.
- Create a VCD file (I use GHDL, but Verilog tools should work too) which records the timing behavior of the signals you care about
- Create a JSON config file which associates the VCD signal names with the SVG groups
- Run the
animatetiming.py
script
-
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Make animated digital logic diagrams using VHDL, SVG, and Python
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Make animated digital logic diagrams using VHDL, SVG, and Python
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