Skip to content

Make animated digital logic diagrams using VHDL, SVG, and Python

License

Notifications You must be signed in to change notification settings

stevenbell/animatetiming

Repository files navigation

Dependencies

Steps

  1. Create an SVG file where each circuit node is in an SVG group, and give the group a unique (hopefully meaningful) name.
  2. Create a VCD file (I use GHDL, but Verilog tools should work too) which records the timing behavior of the signals you care about
  3. Create a JSON config file which associates the VCD signal names with the SVG groups
  4. Run the animatetiming.py script

About

Make animated digital logic diagrams using VHDL, SVG, and Python

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published