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Teensy 4.0: Fix UART capability #1650

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Merged
merged 2 commits into from
Mar 13, 2021
Merged

Teensy 4.0: Fix UART capability #1650

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d02c8fd
teensy40: move txBuffer allocation to UART declaration
ardnew Mar 7, 2021
b70bd84
add UART0 as alias for UART1
ardnew Mar 12, 2021
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36 changes: 22 additions & 14 deletions src/machine/board_teensy40.go
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Original file line number Diff line number Diff line change
Expand Up @@ -136,9 +136,11 @@ const (
)

var (
UART0 = &UART1 // alias UART0 to UART1
UART1 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART6,
Bus: nxp.LPUART6,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D0 (PA3 [AD_B0_03])
mux: nxp.IOMUXC_LPUART6_RX_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT2,
sel: &nxp.IOMUXC.LPUART6_RX_SELECT_INPUT,
Expand All @@ -149,8 +151,9 @@ var (
},
}
UART2 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART4,
Bus: nxp.LPUART4,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D7 (PB17 [B1_01])
mux: nxp.IOMUXC_LPUART4_RX_SELECT_INPUT_DAISY_GPIO_B1_01_ALT2,
sel: &nxp.IOMUXC.LPUART4_RX_SELECT_INPUT,
Expand All @@ -161,8 +164,9 @@ var (
},
}
UART3 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART2,
Bus: nxp.LPUART2,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D15 (PA19 [AD_B1_03])
mux: nxp.IOMUXC_LPUART2_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_03_ALT2,
sel: &nxp.IOMUXC.LPUART2_RX_SELECT_INPUT,
Expand All @@ -173,8 +177,9 @@ var (
},
}
UART4 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART3,
Bus: nxp.LPUART3,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D16 (PA23 [AD_B1_07])
mux: nxp.IOMUXC_LPUART3_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_07_ALT2,
sel: &nxp.IOMUXC.LPUART3_RX_SELECT_INPUT,
Expand All @@ -185,8 +190,9 @@ var (
},
}
UART5 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART8,
Bus: nxp.LPUART8,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D21 (PA27 [AD_B1_11])
mux: nxp.IOMUXC_LPUART8_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_11_ALT2,
sel: &nxp.IOMUXC.LPUART8_RX_SELECT_INPUT,
Expand All @@ -197,15 +203,17 @@ var (
},
}
UART6 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART1,
Bus: nxp.LPUART1,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
// LPUART1 not connected via IOMUXC
// RX: D24 (PA12 [AD_B0_12])
// TX: D25 (PA13 [AD_B0_13])
}
UART7 = UART{
Buffer: NewRingBuffer(),
Bus: nxp.LPUART7,
Bus: nxp.LPUART7,
Buffer: NewRingBuffer(),
txBuffer: NewRingBuffer(),
muxRX: muxSelect{ // D28 (PC18 [EMC_32])
mux: nxp.IOMUXC_LPUART7_RX_SELECT_INPUT_DAISY_GPIO_EMC_32_ALT2,
sel: &nxp.IOMUXC.LPUART7_RX_SELECT_INPUT,
Expand Down
8 changes: 4 additions & 4 deletions src/machine/machine_mimxrt1062_uart.go
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,10 @@ type UART struct {
Buffer *RingBuffer
Interrupt interrupt.Interrupt

// txBuffer should be allocated globally (such as when UART is created) to
// prevent it being reclaimed or cleaned up prematurely.
txBuffer *RingBuffer

// these hold the input selector ("daisy chain") values that select which pins
// are connected to the LPUART device, and should be defined where the UART
// instance is declared. see the godoc comments on type muxSelect for more
Expand All @@ -31,7 +35,6 @@ type UART struct {
configured bool
msbFirst bool
transmitting volatile.Register32
txBuffer *RingBuffer
}

func (uart *UART) isTransmitting() bool { return uart.transmitting.Get() != 0 }
Expand Down Expand Up @@ -197,9 +200,6 @@ func (uart *UART) Sync() error {

// WriteByte writes a single byte of data to the UART interface.
func (uart *UART) WriteByte(c byte) error {
if nil == uart.txBuffer {
uart.txBuffer = NewRingBuffer()
}
uart.startTransmitting()
for !uart.txBuffer.Put(c) {
}
Expand Down