Architecture

RMII → MAC → L3/L4 stack → echo. Networking foundation for lab UDP on Nexys A7 — upstream of itch Mold/ITCH ingress.

Hierarchy

Role	Path
Board top	`core/rtl/top.sv`
Stack core	`core/rtl/stack/udp_stack_core.sv`
Sim top	`sim/hdl/udp_loopback_top.sv`

Synthesized hierarchy: top → u_mdio, u_phy, u_mac, u_stack, u_seg7.

RTL schematic — board I/O and PHY/MAC (left) · stack core and RMII egress (right)

rmii_phy_if → eth_mac_axis → udp_stack_core → eth_mac_axis → rmii_phy_if
                              └─ loopback_echo → stack_tx

Inside udp_stack_core:

eth_demux → ip_rx → udp_rx → loopback_echo → axis_fifo → stack_tx

Layer	Module	Role
PHY	`rmii_phy_if`, `lan8720_mdio`	RMII byte stream, MDIO link status
L2	`eth_mac_axis`	Preamble/FCS strip, CRC on TX
L2 demux	`eth_demux`	IPv4 forward; ARP ethertype detect
L3	`ip_rx`	IPv4 header parse, dst-IP filter
L4	`udp_rx`	UDP header parse, dst-port filter (`50000`)
App	`loopback_echo`	Cut-through payload echo + latency counter
TX	`stack_tx`	Rebuild Ethernet / IPv4 / UDP headers
ARP	`arp_cache`	Single-entry stub (lab: pre-seed host MAC in `top.sv`)

RX: MAC strips preamble/FCS; eth_demux forwards IPv4; ip_rx / udp_rx parse headers and filter port 50000.
TX: loopback_echo passes payload cut-through; stack_tx rebuilds headers with swapped src/dst.
ARP: Detected in eth_demux; dynamic lookup not required for lab — set HOST_MAC in top.sv.

Clock	Source	Period
`CLK100MHZ`	Board oscillator	10 ns (100 MHz)
`eth_refclk`	PHY RMII ref	20 ns (50 MHz)

RMII and MDIO pins on the xc7a100tcsg324-1 package (implemented design view):

Package pinout — eth_* RMII/MDIO ports match top.sv and nexys_a7_100t.xdc

Broadcast (255.255.255.255) works for direct-cable tests without ARP.