Numbers below are copied from files in this repo — not estimated. Last Vivado build: 2026-08-10. Screenshots: media/proj_summary.png, media/dashboard.png.
See also: README — at a glance · bitstream
Source: sim/results/latency_summary.json — written by test_loopback_perf in sim/cocotb/test_loopback_perf.py.
| Metric | Budget | Measured |
|---|---|---|
Payload loopback (loopback_echo) @ 100 MHz |
≤ 20 cycles (200 ns) | 2 cycles (20 ns) |
Regenerate:
cd sim/cocotb && python run_tests.pyReports: core/core.runs/impl_1/
Source: top_timing_summary_routed.rpt — Design Timing Summary
| Metric | Value |
|---|---|
| WNS | +1.985 ns |
| TNS | 0.000 ns |
| WHS | +0.037 ns |
| THS | 0.000 ns |
| Failing endpoints | 0 |
Source: top_utilization_placed.rpt (post-place)
| Resource | Used | Util% |
|---|---|---|
| Slice LUTs | 756 | 1.19% |
| Slice FFs | 599 | 0.47% |
| Bonded IOB | 52 | 24.76% |
| BUFG | 2 | 6.25% |
Vivado Project Summary dashboard rounds LUT/FF to 1% and IO to 25% — same build, coarser display.
Left: timing summary (WNS +1.985 ns) · Right: LUT 1%, FF 1%, IO 25%, power 0.115 W
Source: top_power_routed.rpt
| Value | |
|---|---|
| Total on-chip (est.) | 0.115 W |
| Dynamic | 0.018 W |
| Device static | 0.097 W |
| Junction temperature (est.) | 25.5 °C |
Post-route floorplan — logic placement on Artix-7 fabric (same 2026-08-10 build):
Implemented device — stack concentrated in left clock regions; I/O banks at package edges