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Bitstream build

Vivado Artix-7

Synthesis → implementation → bitstream for the Nexys A7 UDP/IP stack.

See also: core/README.md (GUI walkthrough) · metrics · board_setup

Project
Toolchain Vivado 2025.2
Project file core/core.xpr
Top module top
RTL core/rtl/ (15 .sv files)
Constraints core/constrs/nexys_a7_100t.xdc
Part xc7a100tcsg324-1

GUI flow

  1. Open or create project in core/
  2. Add Sources → directory core/rtl/
  3. Set top: top
  4. Add Constraints → core/constrs/nexys_a7_100t.xdc
  5. Run synthesis → implementation → bitstream

Full step-by-step: core/README.md

Output

core/core.runs/impl_1/top.bit

Vivado Hardware Manager — top.bit programmed on xc7a100t_0

Hardware Manager — top.bit from core/core.runs/impl_1/ on xc7a100t_0

Post-route timing and utilization: metrics.md — WNS +1.985 ns @ 100 MHz (2026-08-10 build).

Board test

python tools/send_udp.py --host 255.255.255.255 --port 50000

Bench details: board_setup.md