Interests: speculative superscalar out-of-order cpu microarch, ISA design, memory system, ...
VLSI/ASIC, sync and async (dynamic) logic
- Milpitas, CA, USA
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20:21
(UTC -07:00) - https://chaos.social/@tommythorn
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dromajo
dromajo PublicForked from chipsalliance/dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
C++
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spleentt-5x8-font
spleentt-5x8-font PublicTiny 5x8 bitmap font based on spleen and creep, useful for low-resolution displays
Rust 20
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