#

asic-design

Here are 72 public repositories matching this topic...

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

google / qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

machine-learning fpga deep-learning tensorflow accelerator keras quantization hardware-acceleration fpga-accelerator quantized-neural-networks asic-design quantized-networks

Updated Jun 13, 2025
Python

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Aug 27, 2025
SystemVerilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Oct 21, 2024
Verilog

lirui-shanghaitech / CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

fpga accelerator cnn fpga-accelerator cnn-digital cnn-accelerator asic-design

Updated Apr 10, 2023
Verilog

cpc / openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)

fpga hardware-designs asic-design hardware-accelerators

Updated Sep 9, 2025
C

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Jul 4, 2025
Verilog

thousrm / universal_NPU-CNN_accelerator

hardware design of universal NPU(CNN accelerator) for various convolution neural network

cnn verilog npu cnn-accelerator asic-design hardware-design

Updated Mar 5, 2025
Verilog

librelane / librelane

ASIC implementation flow infrastructure

asic eda digital-design electronic-design-automation asic-design openlane chip-design librelane

Updated Sep 6, 2025
Python

cgra4ml

KastnerRG / cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated May 22, 2025
SystemVerilog

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Apr 20, 2025
Verilog

lethalbit / kicad-pdk-libs

KiCad symbol library for sky130 and gf180mcu PDKs

electronics spice kicad asic-design

Updated Feb 14, 2024
Python

dpretet / friscv

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Sep 2, 2025
SystemVerilog

Lampro-Mellon / Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

torii-hdl

shrine-maiden-heavy-industries / torii-hdl

A Python-based HDL and framework for silicon-based witchcraft

fpga hdl yosys digital-logic-design nextpnr asic-design torii-hdl

Updated Sep 12, 2025
Python

VardhanSuroshi / VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

opensource rtl vlsi risc-v vlsi-physical-design vlsi-design asic-design skywater openlane

Updated Jan 23, 2024
Verilog

meeeeet / RTL-to-GDS-Implementation-of-SerDes

verilog vlsi-physical-design openroad asic-design rtl2gds

Updated Feb 22, 2024
Verilog

dpretet / bster

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut

Updated Sep 5, 2021
SystemVerilog

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

Improve this page

Add a description, image, and links to the asic-design topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the asic-design topic, visit your repo's landing page and select "manage topics."