Lay out decoupling capacitor partitions as uniform banks

[forgehk]

Closes #15

Decoupling-cap partitions (already produced by ChipPartitionsSolver with
partitionType: "decoupling_caps") now skip PackSolver2 and get a
datasheet-style bank layout in SingleInnerPartitionPackingSolver:

• every cap oriented with its VCC pin facing y+ and GND pin facing y-
  (derived from the partition's isPositiveVoltageSource / isGround net
  flags; a flipped-wired cap is rotated 180)
• deterministic natural-sort order, uniform pitch of cap width +
  decouplingCapsGap, VCC pins aligned into a straight rail
• groups larger than 8 wrap into balanced rows

PartitionPackingSolver is unchanged; the bank keeps its real net ids so the
existing network-distance packing pulls it next to the main chip.

Evidence: SVG snapshot tests using graphics-debug/matcher + bun-match-svg
(both already in node_modules as peers of graphics-debug; the bunfig preload
for them was already in the repo, commented out). One unit-level snapshot of
the bank and one full-pipeline snapshot on the LayoutPipelineSolver06 fixture
(RP2040-style chip with 6+2 decoupling caps).

Before (caps in scrambled order: C15 C12 C14 C8 C13 C19):

After (deterministic bank C8 C12 C13 C14 C15 C19, uniform pitch, straight rail):

bun test: 22 pass, 1 skip (pre-existing), 0 fail. No dependency or lockfile
changes.

/claim #15

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[rushabhcodes]

Hey @forgehk , thanks so much for your contribution. Unfortunately, we’ve closed the bounty program, but we really appreciate your effort.