Add LMK1C1104 clock buffer subcircuit - #114
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Summary
ClockBuffer_LMK1C1104, filling theClocks & timing→Clock bufferscategory represented inti-sysblocksCLKIN,OE,VDD,GND, and the four driven outputsY0–Y3throughexposedNets; use connected native<netlabel>elements for the public signal endpoints<schematictext>while omitting their background frames; the Altium sheet border, TI title block/logo, parameter fields, and legal/footer boilerplate are intentionally omittedOEis the public API alias for TI's1Gpin/net label because tscircuit net selectors cannot begin with a digit. The chip symbol still identifies the physical pin as1G.Consumers can instantiate the subcircuit and connect through the exposed parent nets, for example
net.CLKIN,net.OE, andnet.Y0–net.Y3.Reference and conversion
ti-sysblockslists LMK1C1104 under Clocks & timing → Clock buffersHSDC078A_Validation_Board_Schematic.SchDocwas converted withaltium-to-circuit-jsonv0.0.13 (97e5b2e4bb9acba337af0de07d74287e5e089f2a) using:The normalized conversion contains 917 Circuit JSON elements and validates cleanly. Altium stored 49 passive MPNs in
Commentwhile hiding their electrical values inValue; normalization restored those resistor/capacitor values before validation.Provenance hashes:
SNAR039.ZIP:2fd36888e5713ba79fe4f79e41332dc87eed296656d6cd5785cbf95bcabc4781.SchDoc:787e4a3067ffd033d45af0b09c6bccdf704f1e3801d38eaa9f99ae3af644d7614ed3e68e6e4558bf9fbf0a42ccd8b46ad63c5e0bc9d1ef2857f924933399a55cThe Altium PCB document is an unsynchronized 16-pin LMK1C1108 validation layout. The schematic and BOM identify the actual LMK1C1104 as
PW0008ATSSOP-8, so this implementation uses the correct 8-pin footprint and a newly routed PCB snapshot rather than claiming literal PCB reproduction.Validation
bun run typecheckbun run format:checkbunx tsci build lib/subcircuits/ClockBuffer_LMK1C1104.circuit.tsxbunx tsci snapshot lib/subcircuits/ClockBuffer_LMK1C1104.circuit.tsx --test --concurrency 1git diff --check*_errorrecordsThe nested-consumer audit verifies parent connectivity for exactly
CLKIN,OE,VDD,GND, andY0–Y3, while Y4–Y7 remain scoped to their DNP fixtures.The build succeeds. Its remaining placement warnings come from retaining TI's tightly packed validation-fixture geometry; supplier-footprint IoU and unnamed-trace messages are non-fatal.
Related work
Open PR #112 contains a datasheet-derived LMK1C1104 example and a different package variant, but it does not add a reusable component under
lib/subcircuits. This PR uses the TSSOP-8 package from the Altium EVM schematic/BOM.