or gate

// This file implements or gate in different levels of abstraction in different modules. There is testbench for each module which has a particular level of abstraction, these 
//test bench modules test the functionality of the modules that implement the functionality of or gate.

module or1 (y,a,b); // Gate level modelling
input a,b;
output y;
or (y,a,b);
endmodule

module or2(y,a,b); //Dataflow modelling
input a,b;
output y;
assign y=(a|b);
endmodule

module or3(output reg y, input a,input b); //Behavioral modelling
always @ (a or b)
if((a==1'b0)&&(b==1'b0))
y=1'b0;
else if((a==1'b1)||(b==1'b1))
y=1'b1;
else
y=1'bx;
endmodule

module stimulus1;
wire y;
reg a,b;
or1 an(y,a,b);
initial 
begin
$monitor($time,"Output = %b, A = %b, B = %b", y,a,b);
#5 a=1'b0; b=1'b0;
#5 a=1'b1;
#10 a=1'b0; b=1'b1;
#5 a=1'b1;
end
endmodule

module stimulus2;
wire y;
reg a,b;
or2 an(y,a,b);
initial 
begin
$monitor($time,"Output = %b, A = %b, B = %b", y,a,b);
#5 a=1'b0; b=1'b0;
#5 a=1'b1;
#10 a=1'b0; b=1'b1;
#5 a=1'b1;
end
endmodule

module stimulus3;
wire y;
reg a,b;
or3 an(y,a,b);
initial 
begin
$monitor($time,"Output = %b, A = %b, B = %b", y,a,b);
#5 a=1'b0; b=1'b0;
#5 a=1'b1;
#10 a=1'b0; b=1'b1;
#5 a=1'b1;
end
endmodule