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101 Commits
1 - bit magnitude comparator
1 - bit magnitude comparator
 
 
1 : 4 demux using case statements (behavioural modelling)
1 : 4 demux using case statements (behavioural modelling)
 
 
1 digit XS-3 adder
1 digit XS-3 adder
 
 
4 bit binary to gray converter
4 bit binary to gray converter
 
 
4-bit full adder using gate level abstraction
4-bit full adder using gate level abstraction
 
 
4-bit ripple counter ( behavioural modelling)
4-bit ripple counter ( behavioural modelling)
 
 
4-t0-1 mux using dataflow abstraction level
4-t0-1 mux using dataflow abstraction level
 
 
4:1 mux using case statements (behavioural modelling)
4:1 mux using case statements (behavioural modelling)
 
 
4:1 mux using conditional operator(dataflow modelling)
4:1 mux using conditional operator(dataflow modelling)
 
 
4bitcounter.v
4bitcounter.v
 
 
Design_counter.v
Design_counter.v
 
 
IC7420.v
IC7420.v
 
 
NegEdgeCapture.v
NegEdgeCapture.v
 
 
README.md
README.md
 
 
Ringer.v
Ringer.v
 
 
Thermostat.v
Thermostat.v
 
 
Traffic Signal Controller
Traffic Signal Controller
 
 
Truthtable1.v
Truthtable1.v
 
 
UART.sv
UART.sv
 
 
active_low_reset.v
active_low_reset.v
 
 
and gate
and gate
 
 
and gate using Nand gate
and gate using Nand gate
 
 
carrylook ahead adder (4-bit using dataflow modelling)
carrylook ahead adder (4-bit using dataflow modelling)
 
 
cat3.v
cat3.v
 
 
cellular_automation.v
cellular_automation.v
 
 
ckt1.v
ckt1.v
 
 
ckt2.v
ckt2.v
 
 
ckt3.v
ckt3.v
 
 
ckt4.v
ckt4.v
 
 
ckt5.v
ckt5.v
 
 
ckt6.v
ckt6.v
 
 
ckt7.v
ckt7.v
 
 
ckt8.v
ckt8.v
 
 
ckt9.v
ckt9.v
 
 
ckteq.v
ckteq.v
 
 
clock.v
clock.v
 
 
count1to10.v
count1to10.v
 
 
count_ones.v
count_ones.v
 
 
countbcd.v
countbcd.v
 
 
counter1000.v
counter1000.v
 
 
counter3bit.v
counter3bit.v
 
 
countslow.v
countslow.v
 
 
decadecounter.v
decadecounter.v
 
 
decoder 3 to 8
decoder 3 to 8
 
 
demux 1 to 2
demux 1 to 2
 
 
design.v
design.v
 
 
dff.v
dff.v
 
 
dff1.v
dff1.v
 
 
dff2.v
dff2.v
 
 
dff3.v
dff3.v
 
 
dlatch.v
dlatch.v
 
 
edge_detection.v
edge_detection.v
 
 
encoder 4:2
encoder 4:2
 
 
fsm.v
fsm.v
 
 
fsm1.v
fsm1.v
 
 
fsm101.v
fsm101.v
 
 
fsm2.v
fsm2.v
 
 
fsm3.v
fsm3.v
 
 
fsm4.v
fsm4.v
 
 
fsmcomp.v
fsmcomp.v
 
 
fulladder 4-bit using dataflow operators
fulladder 4-bit using dataflow operators
 
 
gate.v
gate.v
 
 
gate1.v
gate1.v
 
 
gates.v
gates.v
 
 
half adder
half adder
 
 
inverter
inverter
 
 
jk.v
jk.v
 
 
jk_using_d.v
jk_using_d.v
 
 
lfsr5.v
lfsr5.v
 
 
mod1000counter.v
mod1000counter.v
 
 
mux 8 to 1
mux 8 to 1
 
 
mux_4-to-1(gate level)
mux_4-to-1(gate level)
 
 
nor gate
nor gate
 
 
or gate
or gate
 
 
or gate using Nand gate
or gate using Nand gate
 
 
overflow detector.v
overflow detector.v
 
 
posedge_detection.v
posedge_detection.v
 
 
posedge_detector.v
posedge_detector.v
 
 
priority encoder 4 : 2
priority encoder 4 : 2
 
 
reverse_vector.v
reverse_vector.v
 
 
rotate100.v
rotate100.v
 
 
shiftcount.v
shiftcount.v
 
 
shiftreg4bit.v
shiftreg4bit.v
 
 
simpleckt.v
simpleckt.v
 
 
simpleckt1.v
simpleckt1.v
 
 
stretch3pulse.v
stretch3pulse.v
 
 
tb.v
tb.v
 
 
tb1.v
tb1.v
 
 
timer.v
timer.v
 
 

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These are codes written for digital blocks in Verilog (HDL) language.

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These are Verilog (HDL) codes.

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verilog verilog-hdl verilog-programs verilog-code uby ubyh

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