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@ucb-bar

UC Berkeley Architecture Research

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  1. chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1.8k 696

  2. chiseltest Public archive

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

    Scala 231 76

  3. dsptools Public

    A Library of Chisel3 Tools for Digital Signal Processing

    Scala 234 39

  4. chisel-tutorial Public

    chisel tutorial exercises and answers

    Scala 720 198

Repositories

Showing 10 of 194 repositories
  • MaDa Public

    A mill based FPGA shell.

    Verilog 2 MIT 0 1 1 Updated Apr 17, 2025
  • HTML 1 11 0 1 Updated Apr 16, 2025
  • zephyr Public Forked from zephyrproject-rtos/zephyr

    Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

    C 0 Apache-2.0 7,272 0 0 Updated Apr 16, 2025
  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 1,815 BSD-3-Clause 696 149 (3 issues need help) 25 Updated Apr 15, 2025
  • libgemmini Public

    Gemmini extensions for Spike

    C++ 2 5 1 0 Updated Apr 15, 2025
  • Baremetal-IDE Public

    A submodule of Chipyard https://github.com/ucb-bar/chipyard

    HTML 10 11 3 1 Updated Apr 14, 2025
  • saturn-vectors Public

    Chisel RISC-V Vector 1.0 Implementation

    Assembly 92 BSD-3-Clause 9 2 0 Updated Apr 14, 2025
  • ara-wrapper Public
    Scala 2 0 0 0 Updated Apr 14, 2025
  • tacit_decoder Public
    Rust 4 0 0 1 Updated Apr 14, 2025
  • tacit Public

    Timing Accurate Core Instruction Trace

    Scala 0 0 0 0 Updated Apr 14, 2025